/*
 * Ingenic JZ MMC support
 *
 * Copyright (c) 2016 Ingenic Semiconductor Co.,Ltd
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __MMC_H__
#define __MMC_H__

#include <asm/arch/base.h>

/* response type*/
#define MSC_CMDAT_RESPONSE_NONE    (0x0) /* No response */
#define MSC_CMDAT_RESPONSE_R1      (0x1) /* Format R1 , R3, R6, R7 length 48 */
#define MSC_CMDAT_RESPONSE_R1b     (0x2) /* Format R1b length 48 */
#define MSC_CMDAT_RESPONSE_R2      (0x3) /* Format R2 length 136 */
#define MSC_CMDAT_RESPONSE_R3      (0x4) /* Format R3 length 48 */
#define MSC_CMDAT_RESPONSE_R4      (0x5) /* Format R4 length 48 */
#define MSC_CMDAT_RESPONSE_R5      (0x6) /* Format R5 length 48 */
#define MSC_CMDAT_RESPONSE_R6      (0x7) /* Format R6 length 48 */
#define MSC_CMDAT_RESPONSE_R7      (0x8) /* Format R7 length 48 */


#define BIT(nr)         (1UL << (nr))
#define GENMASK(h, l) \
    (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))

/**
 * MSC Register Offset
 */

#define MSC_SDMASA_R						(0x0)
#define MSC_BLOCKSIZE_R					(0x4)
#define MSC_BLOCKCOUNT_R					(0x6)
#define MSC_ARGUMENT_R						(0x8)
#define MSC_XFER_MODE_R					(0xc)
#define MSC_CMD_R							(0xe)
#define MSC_RESP01_R						(0x10)
#define MSC_RESP23_R						(0x14)
#define MSC_RESP45_R						(0x18)
#define MSC_RESP67_R						(0x1c)
#define MSC_BUF_DATA_R						(0x20)
#define MSC_PSTATE_REG						(0x24)
#define MSC_HOST_CTRL1_R					(0x28)
#define MSC_PWR_CTRL_R						(0x29)
#define MSC_BGAP_CTRL_R					(0x2a)
#define MSC_WUP_CTRL_R						(0x2b)
#define MSC_CLK_CTRL_R						(0x2c)
#define MSC_TOUT_CTRL_R					(0x2e)
#define MSC_SW_RST_R						(0x2f)
#define MSC_NORMAL_INT_STAT_R				(0x30)
#define MSC_ERROR_INT_STAT_R				(0x32)
#define MSC_NORMAL_INT_STAT_EN_R			(0x34)
#define MSC_ERROR_INT_STAT_EN_R			(0x36)
#define MSC_NORMAL_INT_SIGNAL_EN_R			(0x38)
#define MSC_ERROR_INT_SIGNAL_EN_R			(0x3a)
#define MSC_AUTO_CMD_STAT_R				(0x3c)
#define MSC_HOST_CTRL2_R					(0x3e)
#define MSC_CAPABILITIES1_R				(0x40)
#define MSC_CAPABILITIES2_R				(0x44)
#define MSC_CURR_CAPABILITIES1_R			(0x48)
#define MSC_CURR_CAPABILITIES2_R			(0x4c)
#define MSC_FORCE_AUTO_CMD_STAT_R			(0x50)
#define MSC_FORCE_ERROR_INT_STAT_R			(0x52)
#define MSC_ADMA_ERR_STAT_R				(0x54)
#define MSC_ADMA_SA_LOW_R					(0x58)
#define MSC_ADMA_SA_HIGH_R					(0x5c)
#define MSC_PRESET_INIT_R					(0x60)
#define MSC_PRESET_DS_R					(0x62)
#define MSC_PRESET_HS_R					(0x64)
#define MSC_PRESET_SDR12_R					(0x66)
#define MSC_PRESET_SDR25_R					(0x68)
#define MSC_PRESET_SDR50_R					(0x6a)
#define MSC_PRESET_SDR104_R				(0x6c)
#define MSC_PRESET_DDR50_R					(0x6e)
#define MSC_ADMA_ID_LOW_R					(0x78)
#define MSC_ADMA_ID_HIGH_R					(0x7c)
#define MSC_P_EMBEDDED_CNTRL				(0xe6)
#define MSC_P_VENDOR_SPECIFIC_AREA			(0xe8)
#define MSC_P_VENDOR2_SPECIFIC_AREA		(0xea)
#define MSC_SLOT_INTR_STATUS_R				(0xfc)
#define MSC_HOST_CNTRL_VERS_R				(0xfe)

#define MSC_EMBEDDED_CTRL_R				(0x0)

#define MSC_CQVER							(0x0)
#define MSC_CQCAP							(0x4)
#define MSC_CQCFG							(0x8)
#define MSC_CQIS							(0x10)
#define MSC_CQISE							(0x14)
#define MSC_CQISGE							(0x18)
#define MSC_CQIC							(0x1c)
#define MSC_CQTDLBA						(0x20)
#define MSC_CQTDBR							(0x28)
#define MSC_CQTCN							(0x2c)
#define MSC_CQDQS							(0x30)
#define MSC_CQDPT							(0x34)
#define	MSC_CQTCLR							(0x38)
#define MSC_CQSSC1							(0x40)
#define MSC_CQSSC2							(0x44)
#define MSC_CQCRDCT						(0x48)
#define MSC_CQRMEM							(0x50)
#define MSC_CQTERRI						(0x54)
#define MSC_CQCRI							(0x58)
#define MSC_CQCRA							(0x5c)

#define MSC_VER_ID_R						(0x0)
#define MSC_VER_TYPE_R						(0x4)
#define MSC_EMMC_CTRL_R					(0x2c)
#define MSC_BOOT_CTRL_R					(0x2e)
#define MSC_GP_IN_R						(0x30)
#define MSC_GP_OUT_R						(0x34)

/**
 * MSC Register Bit Field Define
 */

/* BLOCKSIZE_R */
#define MSC_SDMA_BUF_BDARY_HBIT			(14)
#define MSC_SDMA_BUF_BDARY_LBIT			(12)
#define MSC_SDMA_BUF_BDARY_MASK			GENMASK(MSC_SDMA_BUF_BDARY_HBIT, MSC_SDMA_BUF_BDARY_LBIT)
#define MSC_SDMA_BUF_BDARY_BYTES_4K		(0x0 << MSC_SDMA_BUF_BDARY_LBIT)
#define MSC_SDMA_BUF_BDARY_BYTES_8K		(0x1 << MSC_SDMA_BUF_BDARY_LBIT)
#define MSC_SDMA_BUF_BDARY_BYTES_16K		(0x2 << MSC_SDMA_BUF_BDARY_LBIT)
#define MSC_SDMA_BUF_BDARY_BYTES_32K		(0x3 << MSC_SDMA_BUF_BDARY_LBIT)
#define MSC_SDMA_BUF_BDARY_BYTES_64K		(0x4 << MSC_SDMA_BUF_BDARY_LBIT)
#define MSC_SDMA_BUF_BDARY_BYTES_128K		(0x5 << MSC_SDMA_BUF_BDARY_LBIT)
#define MSC_SDMA_BUF_BDARY_BYTES_256K		(0x6 << MSC_SDMA_BUF_BDARY_LBIT)
#define MSC_SDMA_BUF_BDARY_BYTES_512K		(0x7 << MSC_SDMA_BUF_BDARY_LBIT)

#define MSC_XFER_BLOCK_SIZE_HBIT			(11)
#define MSC_XFER_BLOCK_SIZE_LBIT			(0)
#define MSC_XFER_BLOCK_SIZE_MASK			GENMASK(MSC_XFER_BLOCK_SIZE_HBIT, MSC_XFER_BLOCK_SIZE_LBIT)

/* XFER_MODE_R */
#define MSC_RESP_INT_DISABLE_BIT			BIT(8)
#define MSC_RESP_INT_ENABLE				(0)
#define MSC_RESP_INT_DISABLE				(1)

#define MSC_RESP_ERR_CHK_ENABLE_BIT		BIT(7)
#define MSC_RESP_ERR_CHK_ENABLE			(0)
#define MSC_RESP_ERR_CHK_DISABLE			(1)

#define MSC_RESP_TYPE_BIT					BIT(6)
#define MSC_RESP_TYPE_R1					(0)
#define MSC_RESP_TYPE_R5					(1)

#define MSC_MULTI_BLK_SEL_BIT				BIT(5)
#define MSC_MULTI_BLK_SEL_SINGLE			(0)
#define MSC_MULTI_BLK_SEL_MULTI			(1)

#define MSC_DATA_XFER_DIR_BIT				BIT(4)
#define MSC_DATA_XFER_DIR_WR				(0)
#define MSC_DATA_XFER_DIR_RD				(1)

#define MSC_AUTO_CMD_ENABLE_HBIT			(3)
#define MSC_AUTO_CMD_ENABLE_LBIT			(2)
#define MSC_AUTO_CMD_ENABLE_MASK			GENMASK(MSC_AUTO_CMD_ENABLE_HBIT, MSC_AUTO_CMD_ENABLE_LBIT)
#define MSC_AUTO_CMD_DISABLE				(0x0 << MSC_AUTO_CMD_ENABLE_LBIT)
#define MSC_AUTO_CMD12_ENABLE				(0x1 << MSC_AUTO_CMD_ENABLE_LBIT)
#define MSC_AUTO_CMD23_ENABLE				(0x2 << MSC_AUTO_CMD_ENABLE_LBIT)
#define MSC_AUTO_CMD_AUTO_SEL				(0x3 << MSC_AUTO_CMD_ENABLE_LBIT)

#define MSC_BLOCK_COUNT_ENABLE_BIT			BIT(1)
#define MSC_BLOCK_COUNT_DISABLE			(0)
#define MSC_BLOCK_COUNT_ENABLE				(1)

#define MSC_DMA_ENABLE_BIT					BIT(0)
#define MSC_DMA_DISABLE					(0)
#define MSC_DMA_ENABLE						(1)

/* CMD_R */
#define MSC_CMD_INDEX_HBIT					(13)
#define MSC_CMD_INDEX_LBIT					(8)
#define MSC_CMD_INDEX_MASK					GENMASK(MSC_CMD_INDEX_HBIT, MSC_CMD_INDEX_LBIT)

#define MSC_CMD_TYPE_HBIT					(7)
#define MSC_CMD_TYPE_LBIT					(6)
#define MSC_CMD_TYPE_MASK					GENMASK(MSC_CMD_INDEX_HBIT, MSC_CMD_INDEX_LBIT)
#define	MSC_CMD_TYPE_NORMAL_CMD			(0x0 << MSC_CMD_TYPE_LBIT)
#define MSC_CMD_TYPE_SUSPEND_CMD			(0x1 << MSC_CMD_TYPE_LBIT)
#define MSC_CMD_TYPE_RESUME_CMD			(0x2 << MSC_CMD_TYPE_LBIT)
#define MSC_CMD_TYPE_ABORT_CMD				(0x3 << MSC_CMD_TYPE_LBIT)

#define MSC_DATA_PRESENT_SEL_BIT			BIT(5)
#define MSC_DATA_PRESENT_SEL_NO_DATA		(0)
#define MSC_DATA_PRESENT_SEL_DATA			(1)

#define MSC_CMD_IDX_CHK_ENABLE_BIT			BIT(4)
#define MSC_CMD_IDX_CHK_DISABLE			(0)
#define MSC_CMD_IDX_CHK_ENABLE				(1)

#define MSC_CMD_CRC_CHK_ENABLE_BIT			BIT(3)
#define MSC_CMD_CRC_CHK_DISABLE			(0)
#define MSC_CMD_CRC_CHK_ENABLE				(1)

#define MSC_SUB_CMD_FLAG_BIT				BIT(2)
#define MSC_SUB_CMD_FLAG_MAIN				(0)
#define MSC_SUB_CMD_FLAG_SUB				(1)

#define MSC_RESP_TYPE_SELECT_HBIT			(1)
#define MSC_RESP_TYPE_SELECT_LBIT			(0)
#define MSC_RESP_TYPE_SELECT_MASK			GENMASK(MSC_RESP_TYPE_SELECT_HBIT, MSC_RESP_TYPE_SELECT_LBIT)
#define MSC_RESP_TYPE_SELECT_NO_RESP		(0x0 << MSC_RESP_TYPE_SELECT_LBIT)
#define MSC_RESP_TYPE_SELECT_RESP_LEN_136	(0x1 << MSC_RESP_TYPE_SELECT_LBIT)
#define MSC_RESP_TYPE_SELECT_RESP_LEN_48	(0x2 << MSC_RESP_TYPE_SELECT_LBIT)
#define MSC_RESP_TYPE_SELECT_RESP_LEN_48B	(0x3 << MSC_RESP_TYPE_SELECT_LBIT)

/* PSTATE_REG */
#define MSC_UHS2_IF_DETECT_BIT				BIT(31)
#define MSC_UHS2_IF_DETECT_FALSE			(0)
#define MSC_UHS2_IF_DETECT_TRUE			(1)

#define MSC_LANE_SYNC_BIT					BIT(30)
#define MSC_LANE_SYNC_FALSE				(0)
#define MSC_LANE_SYNC_TRUE					(1)

#define MSC_IN_DORMANT_ST_BIT				BIT(29)
#define MSC_IN_DORMANT_ST_FALSE			(0)
#define MSC_IN_DORMANT_ST_TRUE				(1)

#define MSC_SUB_CMD_STAT_BIT				BIT(28)
#define MSC_SUB_CMD_STAT_FALSE				(0)
#define MSC_SUB_CMD_STAT_TRUE				(1)

#define MSC_CMD_ISSUE_ERR_BIT				BIT(27)
#define MSC_CMD_ISSUE_ERR_FALSE			(0)
#define MSC_CMD_ISSUE_ERR_TRUE				(1)

#define MSC_HOST_REG_VOL_BIT				BIT(25)
#define MSC_HOST_REG_VOL_FALSE				(0)
#define MSC_HOST_REG_VOL_TRUE				(1)

#define MSC_CMD_LINE_LVL_BIT				BIT(24)

#define MSC_DAT_3_0_HBIT					(23)
#define MSC_DAT_3_0_LBIT					(20)
#define MSC_DAT_3_0_MASK					GENMASK(MSC_DAT_3_0_HBIT, MSC_DAT_3_0_LBIT)

#define MSC_WR_PROTECT_SW_LVL_BIT			BIT(19)
#define MSC_WR_PROTECT_SW_LVL_FALSE		(0)
#define MSC_WR_PROTECT_SW_LVL_TRUE			(1)

#define MSC_CARD_DETECT_PIN_LEVEL_BIT		BIT(18)
#define MSC_CARD_DETECT_PIN_LEVEL_FALSE	(0)
#define MSC_CARD_DETECT_PIN_LEVEL_TRUE		(1)

#define MSC_CARD_STABLE_BIT				BIT(17)
#define MSC_CARD_STABLE_FALSE				(0)
#define MSC_CARD_STABLE_TRUE				(1)

#define MSC_CARD_INSERTED_BIT				BIT(16)
#define MSC_CARD_INSERTED_FALSE			(0)
#define MSC_CARD_INSERTED_TRUE				(1)

#define MSC_BUF_RD_ENABLE_BIT				BIT(11)
#define MSC_BUF_RD_DISABLE					(0)
#define MSC_BUF_RD_ENABLE					(1)

#define MSC_BUF_WR_ENABLE_BIT				BIT(10)
#define MSC_BUF_WR_DISABLE					(0)
#define MSC_BUF_WR_ENABLE					(1)

#define MSC_RD_XFER_ACTIVE_BIT				BIT(9)
#define MSC_RD_XFER_INACTIVE				(0)
#define MSC_RD_XFER_ACTIVE					(1)

#define MSC_WR_XFER_ACTIVE_BIT				BIT(8)
#define MSC_WR_XFER_INACTIVE				(0)
#define MSC_WR_XFER_ACTIVE					(1)

#define MSC_DAT_7_4_HBIT					(7)
#define MSC_DAT_7_4_LBIT					(4)
#define MSC_DAT_7_4_MASK					GENMASK(MSC_DAT_7_4_HBIT, MSC_DAT_7_4_LBIT)

#define MSC_RE_TUNE_REQ_BIT				BIT(3)
#define MSC_RE_TUNE_REQ_FIXED				(0)
#define MSC_RE_TUNE_REQ_RE_TUNE			(1)

#define MSC_DAT_LINE_ACTIVE_BIT			BIT(2)
#define MSC_DAT_LINE_INACTIVE				(0)
#define MSC_DAT_LINE_ACTIVE				(1)

#define MSC_CMD_INHIBIT_DAT_BIT			BIT(1)
#define MSC_CMD_INHIBIT_DAT_READY			(0)
#define MSC_CMD_INHIBIT_DAT_NOT_READY		(1)

#define MSC_CMD_INHIBIT_BIT				BIT(0)
#define MSC_CMD_INHIBIT_READY				(0)
#define MSC_CMD_INHIBIT_NOT_READY			(1)

/* HOST_CTRL1_R */
#define MSC_CARD_DETECT_SIG_LVL_BIT		BIT(7)
#define MSC_CARD_DETECT_SIG_LVL_SDCD_PIN	(0)
#define MSC_CARD_DETECT_SIG_LVL_TEST_LEVEL	(1)

#define MSC_CARD_DETECT_TEST_LVL_BIT		BIT(6)
#define MSC_CARD_DETECT_TEST_LVL_NO_CARD	(0)
#define MSC_CARD_DETECT_TEST_LVL_INSERTED	(1)

#define MSC_EXT_DAT_XFER_BIT				BIT(5)
#define MSC_EXT_DAT_XFER_DEFAULT			(0)
#define MSC_EXT_DAT_XFER_EIGHT_BIT			(1)

#define MSC_DMA_SEL_HBIT					(4)
#define MSC_DMA_SEL_LBIT					(3)
#define MSC_DMA_SEL_MASK					GENMASK(MSC_DMA_SEL_HBIT, MSC_DMA_SEL_LBIT)
#define MSC_DMA_SEL_SDMA					(0x0 << MSC_DMA_SEL_LBIT)
#define MSC_DMA_SEL_RSVD_BIT				(0x1 << MSC_DMA_SEL_LBIT)
#define MSC_DMA_SEL_ADMA2					(0x2 << MSC_DMA_SEL_LBIT)
#define MSC_DMA_SEL_ADMA2_3				(0x3 << MSC_DMA_SEL_LBIT)

#define MSC_HIGH_SPEED_EN_BIT				BIT(2)
#define MSC_HIGH_SPEED_EN_NORMAL			(0)
#define MSC_HIGH_SPEED_EN_HIGH				(1)

#define MSC_DAT_XFER_WIDTH_BIT				BIT(1)
#define MSC_DAT_XFER_WIDTH_BITS_1			(0)
#define MSC_DAT_XFER_WIDTH_BITS_4			(1)

#define MSC_LED_CTRL_BIT					BIT(0)
#define MSC_LED_CTRL_OFF					(0)
#define MSC_LED_CTRL_ON					(1)

/* PWR_CTRL_R */
#define MSC_SD_BUS_VOL_VDD2_HBIT			(7)
#define MSC_SD_BUS_VOL_VDD2_LBIT			(5)
#define MSC_SD_BUS_VOL_VDD2_MASK			GENMASK(MSC_SD_BUS_VOL_VDD2_HBIT, MSC_SD_BUS_VOL_VDD2_LBIT)
#define MSC_SD_BUS_VOL_VDD2_NO_VDD2		(0x0 << MSC_SD_BUS_VOL_VDD2_LBIT)
#define MSC_SD_BUS_VOL_VDD2_RSVD1			(0x1 << MSC_SD_BUS_VOL_VDD2_LBIT)
#define MSC_SD_BUS_VOL_VDD2_RSVD2			(0x2 << MSC_SD_BUS_VOL_VDD2_LBIT)
#define MSC_SD_BUS_VOL_VDD2_RSVD3			(0x3 << MSC_SD_BUS_VOL_VDD2_LBIT)
#define MSC_SD_BUS_VOL_VDD2_V_1_2			(0x4 << MSC_SD_BUS_VOL_VDD2_LBIT)
#define MSC_SD_BUS_VOL_VDD2_V_1_8			(0x5 << MSC_SD_BUS_VOL_VDD2_LBIT)
#define MSC_SD_BUS_VOL_VDD2_NOT_USED6		(0x6 << MSC_SD_BUS_VOL_VDD2_LBIT)
#define MSC_SD_BUS_VOL_VDD2_NOT_USED7		(0x7 << MSC_SD_BUS_VOL_VDD2_LBIT)

#define MSC_SD_BUS_PWR_VDD2_BIT			BIT(4)
#define MSC_SD_BUS_PWR_VDD2_OFF			(0)
#define MSC_SD_BUS_PWR_VDD2_ON				(1)

#define MSC_SD_BUS_VOL_VDD1_HBIT			(3)
#define MSC_SD_BUS_VOL_VDD1_LBIT			(1)
#define MSC_SD_BUS_VOL_VDD1_MASK			GENMASK(MSC_SD_BUS_VOL_VDD1_HBIT, MSC_SD_BUS_VOL_VDD1_LBIT)
#define MSC_SD_BUS_VOL_VDD1_RSVD0			(0x0 << MSC_SD_BUS_VOL_VDD1_LBIT)
#define MSC_SD_BUS_VOL_VDD1_RSVD1			(0x1 << MSC_SD_BUS_VOL_VDD1_LBIT)
#define MSC_SD_BUS_VOL_VDD1_RSVD2			(0x2 << MSC_SD_BUS_VOL_VDD1_LBIT)
#define MSC_SD_BUS_VOL_VDD1_RSVD3			(0x3 << MSC_SD_BUS_VOL_VDD1_LBIT)
#define MSC_SD_BUS_VOL_VDD1_RSVD4			(0x4 << MSC_SD_BUS_VOL_VDD1_LBIT)
#define MSC_SD_BUS_VOL_VDD1_V_1_8			(0x5 << MSC_SD_BUS_VOL_VDD1_LBIT)
#define MSC_SD_BUS_VOL_VDD1_V_3_0			(0x6 << MSC_SD_BUS_VOL_VDD1_LBIT)
#define MSC_SD_BUS_VOL_VDD1_V_3_3			(0x7 << MSC_SD_BUS_VOL_VDD1_LBIT)

#define MSC_SD_BUS_PWR_VDD1_BIT			BIT(0)
#define MSC_SD_BUS_PWR_VDD1_OFF			(0)
#define MSC_SD_BUS_PWR_VDD1_ON				(1)

/* BGAP_CTRL_R */
#define MSC_INT_AT_BGAP_BIT				BIT(3)
#define MSC_INT_AT_BGAP_DISABLE			(0)
#define MSC_INT_AT_BGAP_ENABLE				(1)

#define MSC_RD_WAIT_CTRL_BIT				BIT(2)
#define MSC_RD_WAIT_CTRL_DISABLE			(0)
#define MSC_RD_WAIT_CTRL_ENABLE			(1)

#define MSC_CONTINUE_REQ_BIT				BIT(1)
#define MSC_CONTINUE_REQ_NOT_AFFECT		(0)
#define MSC_CONTINUE_REQ_NOT_RESTART		(1)

#define MSC_STOP_BG_REQ_BIT				BIT(0)
#define MSC_STOP_BG_REQ_XFER				(0)
#define MSC_STOP_BG_REQ_STOP				(1)

/* WUP_CTRL_R */
#define MSC_CARD_REMOVAL_BIT				BIT(2)
#define MSC_CARD_REMOVAL_DISABLE			(0)
#define MSC_CARD_REMOVAL_ENABLE			(1)

#define MSC_CARD_INSERT_BIT				BIT(1)
#define MSC_CARD_INSERT_DISABLE			(0)
#define MSC_CARD_INSERT_ENABLE				(1)

#define MSC_CARD_INT_BIT					BIT(0)
#define MSC_CARD_INT_DISABLE				(0)
#define MSC_CARD_INT_ENABLE				(1)

/* CLK_CTRL_R */
#define MSC_FREQ_SEL_HBIT					(15)
#define MSC_FREQ_SEL_LBIT					(8)
#define MSC_FREQ_SEL_MASK					GENMASK(MSC_FREQ_SEL_HBIT, MSC_FREQ_SEL_LBIT)

#define MSC_UPPER_FREQ_SEL_HBIT			(7)
#define MSC_UPPER_FREQ_SEL_LBIT			(6)
#define MSC_UPPER_FREQ_SEL_MASK			GENMASK(MSC_UPPER_FREQ_SEL_HBIT, MSC_UPPER_FREQ_SEL_LBIT)

#define MSC_CLK_GEN_SELECT_BIT				BIT(5)
#define MSC_CLK_GEN_SELECT_FALSE			(0)
#define MSC_CLK_GEN_SELECT_TRUE			(1)

#define MSC_PLL_ENABLE_BIT					BIT(3)
#define MSC_PLL_ENABLE_FALSE				(0)
#define MSC_PLL_ENABLE_TRUE				(1)

#define MSC_SD_CLK_EN_BIT					BIT(2)
#define MSC_SD_CLK_EN_FALSE				(0)
#define MSC_SD_CLK_EN_TRUE					(1)

#define MSC_INTERNAL_CLK_STABLE_BIT		BIT(1)
#define MSC_INTERNAL_CLK_STABLE_FALSE		(0)
#define MSC_INTERNAL_CLK_STABLE_TRUE		(1)

#define MSC_INTERNAL_CLK_EN_BIT			BIT(0)
#define MSC_INTERNAL_CLK_EN_FALSE			(0)
#define MSC_INTERNAL_CLK_EN_TRUE			(1)

/* TOUT_CTRL_R */
#define MSC_TOUT_CNT_HBIT					(3)
#define MSC_TOUT_CNT_LBIT					(0)
#define MSC_TOUT_CNT_MASK					GENMASK(MSC_TOUT_CNT_HBIT, MSC_TOUT_CNT_LBIT)

/* SW_RST_R */
#define MSC_SW_RST_DAT_BIT					BIT(2)
#define	MSC_SW_RST_DAT_FALSE				(0)
#define MSC_SW_RST_DAT_TRUE				(1)

#define MSC_SW_RST_CMD_BIT					BIT(1)
#define MSC_SW_RST_CMD_FALSE				(0)
#define MSC_SW_RST_CMD_TRUE				(1)

#define MSC_SW_RST_ALL_BIT					BIT(0)
#define MSC_SW_RST_ALL_FALSE				(0)
#define MSC_SW_RST_ALL_TRUE				(1)

/* NORMAL_INT_STAT_R */
#define MSC_ERR_INTERRUPT_STAT_BIT			BIT(15)
#define MSC_ERR_INTERRUPT_STAT_FALSE		(0)
#define MSC_ERR_INTERRUPT_STAT_TRUE		(1)

#define MSC_CQE_EVENT_STAT_BIT				BIT(14)
#define MSC_CQE_EVENT_STAT_FALSE			(0)
#define MSC_CQE_EVENT_STAT_TRUE			(1)

#define MSC_FX_EVENT_STAT_BIT				BIT(13)
#define MSC_FX_EVENT_STAT_FALSE			(0)
#define MSC_FX_EVENT_STAT_TRUE				(1)

#define MSC_RE_TUNE_EVENT_STAT_BIT			BIT(12)
#define MSC_RE_TUNE_EVENT_STAT_FALSE		(0)
#define MSC_RE_TUNE_EVENT_STAT_TRUE		(1)

#define MSC_INT_C_STAT_BIT					BIT(11)
#define MSC_INT_C_STAT_FALSE				(0)
#define MSC_INT_C_STAT_TRUE				(1)

#define MSC_INT_B_STAT_BIT					BIT(10)
#define MSC_INT_B_STAT_FALSE				(0)
#define MSC_INT_B_STAT_TRUE				(1)

#define MSC_INT_A_STAT_BIT					BIT(9)
#define MSC_INT_A_STAT_FALSE				(0)
#define MSC_INT_A_STAT_TRUE				(1)

#define MSC_CARD_INTERRUPT_STAT_BIT		BIT(8)
#define MSC_CARD_INTERRUPT_STAT_FALSE		(0)
#define MSC_CARD_INTERRUPT_STAT_TRUE		(1)

#define MSC_CARD_REMOVAL_STAT_BIT			BIT(7)
#define MSC_CARD_REMOVAL_STAT_FALSE		(0)
#define MSC_CARD_REMOVAL_STAT_TRUE			(1)

#define MSC_CARD_INSERTION_STAT_BIT		BIT(6)
#define MSC_CARD_INSERTION_STAT_FALSE		(0)
#define MSC_CARD_INSERTION_STAT_TRUE		(1)

#define MSC_BUF_RD_READY_STAT_BIT			BIT(5)
#define MSC_BUF_RD_READY_STAT_FALSE		(0)
#define MSC_BUF_RD_READY_STAT_TRUE			(1)

#define MSC_BUF_WR_READY_STAT_BIT			BIT(4)
#define MSC_BUF_WR_READY_STAT_FALSE		(0)
#define MSC_BUF_WR_READY_STAT_TRUE			(1)

#define MSC_DMA_INTERRUPT_STAT_BIT			BIT(3)
#define MSC_DMA_INTERRUPT_STAT_FALSE		(0)
#define MSC_DMA_INTERRUPT_STAT_TRUE		(1)

#define MSC_BGAP_EVENT_STAT_BIT			BIT(2)
#define MSC_BGAP_EVENT_STAT_FALSE			(0)
#define MSC_BGAP_EVENT_STAT_TRUE			(1)

#define MSC_XFER_COMPLETE_STAT_BIT			BIT(1)
#define MSC_XFER_COMPLETE_STAT_FALSE		(0)
#define MSC_XFER_COMPLETE_STAT_TRUE		(1)

#define MSC_CMD_COMPLETE_STAT_BIT			BIT(0)
#define MSC_CMD_COMPLETE_STAT_FALSE		(0)
#define MSC_CMD_COMPLETE_STAT_TRUE			(1)

/* ERROR_INT_STAT_R */
#define MSC_VENDOR_ERR3_STAT_BIT			BIT(15)
#define MSC_VENDOR_ERR3_STAT_FALSE			(0)
#define MSC_VENDOR_ERR3_STAT_TRUE			(1)

#define MSC_VENDOR_ERR2_STAT_BIT			BIT(14)
#define MSC_VENDOR_ERR2_STAT_FALSE			(0)
#define MSC_VENDOR_ERR2_STAT_TRUE			(1)

#define MSC_VENDOR_ERR1_STAT_BIT			BIT(13)
#define MSC_VENDOR_ERR1_STAT_FALSE			(0)
#define MSC_VENDOR_ERR1_STAT_TRUE			(1)

#define MSC_BOOT_ACK_ERR_STAT_BIT			BIT(12)
#define MSC_BOOT_ACK_ERR_STAT_FALSE		(0)
#define MSC_BOOT_ACK_ERR_STAT_TRUE			(1)

#define MSC_RESP_ERR_STAT_BIT				BIT(11)
#define MSC_RESP_ERR_STAT_FALSE			(0)
#define MSC_RESP_ERR_STAT_TRUE				(1)

#define MSC_TUNING_ERR_STAT_BIT			BIT(10)
#define MSC_TUNING_ERR_STAT_FALSE			(0)
#define MSC_TUNING_ERR_STAT_TRUE			(1)

#define MSC_ADMA_ERR_STAT_BIT				BIT(9)
#define MSC_ADMA_ERR_STAT_FALSE			(0)
#define MSC_ADMA_ERR_STAT_TRUE				(1)

#define MSC_AUTO_CMD_ERR_STAT_BIT			BIT(8)
#define MSC_AUTO_CMD_ERR_STAT_FALSE		(0)
#define MSC_AUTO_CMD_ERR_STAT_TRUE			(1)

#define MSC_CUR_LMT_ERR_STAT_BIT			BIT(7)
#define MSC_CUR_LMT_ERR_STAT_FALSE			(0)
#define MSC_CUR_LMT_ERR_STAT_TRUE			(1)

#define MSC_DATA_END_BIT_ERR_STAT_BIT		BIT(6)
#define MSC_DATA_END_BIT_ERR_STAT_FALSE	(0)
#define MSC_DATA_END_BIT_ERR_STAT_TRUE		(1)

#define MSC_DATA_CRC_ERR_STAT_BIT			BIT(5)
#define MSC_DATA_CRC_ERR_STAT_FALSE		(0)
#define MSC_DATA_CRC_ERR_STAT_TRUE			(1)

#define MSC_DATA_TOUT_ERR_STAT_BIT			BIT(4)
#define MSC_DATA_TOUT_ERR_STAT_FALSE		(0)
#define MSC_DATA_TOUT_ERR_STAT_TRUE		(1)

#define MSC_CMD_IDX_ERR_STAT_BIT			BIT(3)
#define MSC_CMD_IDX_ERR_STAT_FALSE			(0)
#define MSC_CMD_IDX_ERR_STAT_TRUE			(1)

#define MSC_CMD_END_BIT_ERR_STAT_BIT		BIT(2)
#define MSC_CMD_END_BIT_ERR_STAT_FALSE		(0)
#define MSC_CMD_END_BIT_ERR_STAT_TRUE		(1)

#define MSC_CMD_CRC_ERR_STAT_BIT			BIT(1)
#define MSC_CMD_CRC_ERR_STAT_FALSE			(0)
#define MSC_CMD_CRC_ERR_STAT_TRUE			(1)

#define MSC_CMD_TOUT_ERR_STAT_BIT			BIT(0)
#define MSC_CMD_TOUT_ERR_STAT_FALSE		(0)
#define MSC_CMD_TOUT_ERR_STAT_TRUE			(1)

/* NORMAL_INT_STAT_EN_R */
#define MSC_CQE_EVENT_STAT_EN_BIT			BIT(14)
#define MSC_CQE_EVENT_STAT_EN_FALSE		(0)
#define MSC_CQE_EVENT_STAT_EN_TRUE			(1)

#define MSC_FX_EVENT_STAT_EN_BIT			BIT(13)
#define MSC_FX_EVENT_STAT_EN_FALSE			(0)
#define MSC_FX_EVENT_STAT_EN_TRUE			(1)

#define MSC_RE_TUNE_EVENT_STAT_EN_BIT		BIT(12)
#define MSC_RE_TUNE_EVENT_STAT_EN_FALSE	(0)
#define MSC_RE_TUNE_EVENT_STAT_EN_TRUE		(1)

#define MSC_INT_C_EVENT_STAT_EN_BIT		BIT(11)
#define MSC_INT_C_EVENT_STAT_EN_FALSE		(0)
#define MSC_INT_C_EVENT_STAT_EN_TRUE		(1)

#define MSC_INT_B_EVENT_STAT_EN_BIT		BIT(10)
#define MSC_INT_B_EVENT_STAT_EN_FALSE		(0)
#define MSC_INT_B_EVENT_STAT_EN_TRUE		(1)

#define MSC_INT_A_EVENT_STAT_EN_BIT		BIT(9)
#define MSC_INT_A_EVENT_STAT_EN_FALSE		(0)
#define MSC_INT_A_EVENT_STAT_EN_TRUE		(1)

#define MSC_CARD_INTERRUPT_STAT_EN_BIT		BIT(8)
#define MSC_CARD_INTERRUPT_STAT_EN_FALSE	(0)
#define MSC_CARD_INTERRUPT_STAT_EN_TRUE	(1)

#define MSC_CARD_REMOVAL_STAT_EN_BIT		BIT(7)
#define MSC_CARD_REMOVAL_STAT_EN_FALSE		(0)
#define MSC_CARD_REMOVAL_STAT_EN_TRUE		(1)

#define MSC_CARD_INSERTION_STAT_EN_BIT		BIT(6)
#define MSC_CARD_INSERTION_STAT_EN_FALSE	(0)
#define MSC_CARD_INSERTION_STAT_EN_TRUE	(1)

#define MSC_BUF_RD_READY_STAT_EN_BIT		BIT(5)
#define MSC_BUF_RD_READY_STAT_EN_FALSE		(0)
#define MSC_BUF_RD_READY_STAT_EN_TRUE		(1)

#define MSC_BUF_WR_READY_STAT_EN_BIT		BIT(4)
#define MSC_BUF_WR_READY_STAT_EN_FALSE		(0)
#define MSC_BUF_WR_READY_STAT_EN_TRUE		(1)

#define MSC_DMA_INTERRUPT_STAT_EN_BIT		BIT(3)
#define MSC_DMA_INTERRUPT_STAT_EN_FALSE	(0)
#define MSC_DMA_INTERRUPT_STAT_EN_TRUE		(1)

#define MSC_BGAP_EVENT_STAT_EN_BIT			BIT(2)
#define MSC_BGAP_EVENT_STAT_EN_FALSE		(0)
#define MSC_BGAP_EVENT_STAT_EN_TRUE		(1)

#define MSC_XFER_COMPLETE_STAT_EN_BIT		BIT(1)
#define MSC_XFER_COMPLETE_STAT_EN_FALSE	(0)
#define MSC_XFER_COMPLETE_STAT_EN_TRUE		(1)

#define MSC_CMD_COMPLETE_STAT_EN_BIT		BIT(0)
#define MSC_CMD_COMPLETE_STAT_EN_FALSE		(0)
#define MSC_CMD_COMPLETE_STAT_EN_TRUE		(1)

/* ERROR_INT_STAT_EN_R */
#define MSC_VENDOR_ERR3_STAT_EN_BIT		BIT(15)
#define MSC_VENDOR_ERR3_STAT_EN_FALSE		(0)
#define MSC_VENDOR_ERR3_STAT_EN_TRUE		(1)

#define MSC_VENDOR_ERR2_STAT_EN_BIT		BIT(14)
#define MSC_VENDOR_ERR2_STAT_EN_FALSE		(0)
#define MSC_VENDOR_ERR2_STAT_EN_TRUE		(1)

#define MSC_VENDOR_ERR1_STAT_EN_BIT		BIT(13)
#define MSC_VENDOR_ERR1_STAT_EN_FALSE		(0)
#define MSC_VENDOR_ERR1_STAT_EN_TRUE		(1)

#define MSC_BOOT_ACK_ERR_STAT_EN_BIT		BIT(12)
#define MSC_BOOT_ACK_ERR_STAT_EN_FALSE		(0)
#define MSC_BOOT_ACK_ERR_STAT_EN_TRUE		(1)

#define MSC_RESP_ERR_STAT_EN_BIT			BIT(11)
#define MSC_RESP_ERR_STAT_EN_FALSE			(0)
#define MSC_RESP_ERR_STAT_EN_TRUE			(1)

#define MSC_TUNING_ERR_STAT_EN_BIT			BIT(10)
#define MSC_TUNING_ERR_STAT_EN_FALSE		(0)
#define MSC_TUNING_ERR_STAT_EN_TRUE		(1)

#define MSC_ADMA_ERR_STAT_EN_BIT			BIT(9)
#define MSC_ADMA_ERR_STAT_EN_FALSE			(0)
#define MSC_ADMA_ERR_STAT_EN_TRUE			(1)

#define MSC_AUTO_CMD_ERR_STAT_EN_BIT		BIT(8)
#define MSC_AUTO_CMD_ERR_STAT_EN_FALSE		(0)
#define MSC_AUTO_CMD_ERR_STAT_EN_TRUE		(1)

#define MSC_CUR_LMT_ERR_STAT_EN_BIT		BIT(7)
#define MSC_CUR_LMT_ERR_STAT_EN_FALSE		(0)
#define MSC_CUR_LMT_ERR_STAT_EN_TRUE		(1)

#define MSC_DATA_END_BIT_ERR_STAT_EN_BIT	BIT(6)
#define MSC_DATA_END_BIT_ERR_STAT_EN_FALSE	(0)
#define MSC_DATA_END_BIT_ERR_STAT_EN_TRUE	(1)

#define MSC_DATA_CRC_ERR_STAT_EN_BIT		BIT(5)
#define MSC_DATA_CRC_ERR_STAT_EN_FALSE		(0)
#define MSC_DATA_CRC_ERR_STAT_EN_TRUE		(1)

#define MSC_DATA_TOUT_ERR_STAT_EN_BIT		BIT(4)
#define MSC_DATA_TOUT_ERR_STAT_EN_FALSE	(0)
#define MSC_DATA_TOUT_ERR_STAT_EN_TRUE		(1)

#define MSC_CMD_IDX_ERR_STAT_EN_BIT		BIT(3)
#define MSC_CMD_IDX_ERR_STAT_EN_FALSE		(0)
#define MSC_CMD_IDX_ERR_STAT_EN_TRUE		(1)

#define MSC_CMD_END_BIT_ERR_STAT_EN_BIT	BIT(2)
#define MSC_CMD_END_BIT_ERR_STAT_EN_FALSE	(0)
#define MSC_CMD_END_BIT_ERR_STAT_EN_TRUE 	(1)

#define MSC_CMD_CRC_ERR_STAT_EN_BIT		BIT(1)
#define MSC_CMD_CRC_ERR_STAT_EN_FALSE		(0)
#define MSC_CMD_CRC_ERR_STAT_EN_TRUE		(1)

#define MSC_CMD_TOUT_ERR_STAT_EN_BIT		BIT(0)
#define MSC_CMD_TOUT_ERR_STAT_EN_FALSE		(0)
#define MSC_CMD_TOUT_ERR_STAT_EN_TRUE		(1)

/* NORMAL_INT_SIGNAL_EN_R */
#define MSC_CQE_EVENT_SIGNAL_EN_BIT		BIT(14)
#define MSC_CQE_EVENT_SIGNAL_EN_FALSE		(0)
#define MSC_CQE_EVENT_SIGNAL_EN_TRUE		(1)

#define MSC_FX_EVENT_SIGNAL_EN_BIT			BIT(13)
#define MSC_FX_EVENT_SIGNAL_EN_FALSE		(0)
#define MSC_FX_EVENT_SIGNAL_EN_TRUE		(1)

#define MSC_RE_TUNE_EVENT_SIGNAL_EN_BIT	BIT(12)
#define MSC_RE_TUNE_EVENT_SIGNAL_EN_FALSE	(0)
#define MSC_RE_TUNE_EVENT_SIGNAL_EN_TRUE	(1)

#define MSC_INT_C_EVENT_SIGNAL_EN_BIT		BIT(11)
#define MSC_INT_C_EVENT_SIGNAL_EN_FALSE	(0)
#define MSC_INT_C_EVENT_SIGNAL_EN_TRUE		(1)

#define MSC_INT_B_EVENT_SIGNAL_EN_BIT		BIT(10)
#define MSC_INT_B_EVENT_SIGNAL_EN_FALSE	(0)
#define MSC_INT_B_EVENT_SIGNAL_EN_TRUE		(1)

#define MSC_INT_A_EVENT_SIGNAL_EN_BIT		BIT(9)
#define MSC_INT_A_EVENT_SIGNAL_EN_FALSE	(0)
#define MSC_INT_A_EVENT_SIGNAL_EN_TRUE		(1)

#define MSC_CARD_INTERRUPT_SIGNAL_EN_BIT	BIT(8)
#define MSC_CARD_INTERRUPT_SIGNAL_EN_FALSE	(0)
#define MSC_CARD_INTERRUPT_SIGNAL_EN_TRUE	(1)

#define MSC_CARD_REMOVAL_SIGNAL_EN_BIT		BIT(7)
#define MSC_CARD_REMOVAL_SIGNAL_EN_FALSE	(0)
#define MSC_CARD_REMOVAL_SIGNAL_EN_TRUE	(1)

#define MSC_CARD_INSERTION_SIGNAL_EN_BIT	BIT(6)
#define MSC_CARD_INSERTION_SIGNAL_EN_FALSE	(0)
#define MSC_CARD_INSERTION_SIGNAL_EN_TRUE	(1)

#define MSC_BUF_RD_READY_SIGNAL_EN_BIT		BIT(5)
#define MSC_BUF_RD_READY_SIGNAL_EN_FALSE	(0)
#define MSC_BUF_RD_READY_SIGNAL_EN_TRUE	(1)

#define MSC_BUF_WR_READY_SIGNAL_EN_BIT		BIT(4)
#define MSC_BUF_WR_READY_SIGNAL_EN_FALSE	(0)
#define MSC_BUF_WR_READY_SIGNAL_EN_TRUE	(1)

#define MSC_DMA_INTERRUPT_SIGANL_EN_BIT	BIT(3)
#define MSC_DMA_INTERRUPT_SIGANL_EN_FALSE	(0)
#define MSC_DMA_INTERRUPT_SIGANL_EN_TRUE	(1)

#define MSC_BGAP_EVENT_SIGNAL_EN_BIT		BIT(2)
#define MSC_BGAP_EVENT_SIGNAL_EN_FALSE		(0)
#define MSC_BGAP_EVENT_SIGNAL_EN_TRUE		(1)

#define MSC_XFER_COMPLETE_SIGNAL_EN_BIT	BIT(1)
#define MSC_XFER_COMPLETE_SIGNAL_EN_FALSE	(0)
#define MSC_XFER_COMPLETE_SIGNAL_EN_TRUE	(1)

#define MSC_CMD_COMPLETE_SIGNAL_EN_BIT		BIT(0)
#define MSC_CMD_COMPLETE_SIGNAL_EN_FALSE	(0)
#define MSC_CMD_COMPLETE_SIGNAL_EN_TRUE	(1)

/* ERROR_INT_SIGNAL_EN_R */
#define MSC_VENDOR_ERR3_SIGNAL_EN_BIT		BIT(15)
#define MSC_VENDOR_ERR3_SIGNAL_EN_FALSE	(0)
#define MSC_VENDOR_ERR3_SIGNAL_EN_TRUE		(1)

#define MSC_VENDOR_ERR2_SIGNAL_EN_BIT		BIT(14)
#define MSC_VENDOR_ERR2_SIGNAL_EN_FALSE	(0)
#define MSC_VENDOR_ERR2_SIGNAL_EN_TRUE		(1)

#define MSC_VENDOR_ERR1_SIGNAL_EN_BIT		BIT(13)
#define MSC_VENDOR_ERR1_SIGNAL_EN_FALSE	(0)
#define MSC_VENDOR_ERR1_SIGNAL_EN_TRUE		(1)

#define MSC_BOOT_ACK_ERR_SIGNAL_EN_BIT		BIT(12)
#define MSC_BOOT_ACK_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_BOOT_ACK_ERR_SIGNAL_EN_TRUE	(1)

#define MSC_RESP_ERR_SIGNAL_EN_BIT			BIT(11)
#define MSC_RESP_ERR_SIGNAL_EN_FALSE		(0)
#define MSC_RESP_ERR_SIGNAL_EN_TRUE		(1)

#define MSC_TUNING_ERR_SIGNAL_EN_BIT		BIT(10)
#define MSC_TUNING_ERR_SIGNAL_EN_FALSE		(0)
#define MSC_TUNING_ERR_SIGNAL_EN_TRUE		(1)

#define MSC_ADMA_ERR_SIGNAL_EN_BIT			BIT(9)
#define MSC_ADMA_ERR_SIGNAL_EN_FALSE		(0)
#define MSC_ADMA_ERR_SIGNAL_EN_TRUE		(1)

#define MSC_AUTO_CMD_ERR_SIGNAL_EN_BIT		BIT(8)
#define MSC_AUTO_CMD_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_AUTO_CMD_ERR_SIGNAL_EN_TRUE	(1)

#define MSC_CUR_LMT_ERR_SIGNAL_EN_BIT		BIT(7)
#define MSC_CUR_LMT_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_CUR_LMT_ERR_SIGNAL_EN_TRUE		(1)

#define MSC_DATA_END_BIT_ERR_SIGNAL_EN_BIT		BIT(6)
#define MSC_DATA_END_BIT_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_DATA_END_BIT_ERR_SIGNAL_EN_TRUE	(1)

#define MSC_DATA_CRC_ERR_SIGNAL_EN_BIT		BIT(5)
#define MSC_DATA_CRC_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_DATA_CRC_ERR_SIGNAL_EN_TRUE	(1)

#define MSC_DATA_TOUT_ERR_SIGNAL_EN_BIT	BIT(4)
#define MSC_DATA_TOUT_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_DATA_TOUT_ERR_SIGNAL_EN_TRUE	(1)

#define MSC_CMD_IDX_ERR_SIGNAL_EN_BIT		BIT(3)
#define MSC_CMD_IDX_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_CMD_IDX_ERR_SIGNAL_EN_TRUE		(1)

#define MSC_CMD_END_BIT_ERR_SIGNAL_EN_BIT		BIT(2)
#define MSC_CMD_END_BIT_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_CMD_END_BIT_ERR_SIGNAL_EN_TRUE 	(1)

#define MSC_CMD_CRC_ERR_SIGNAL_EN_BIT		BIT(1)
#define MSC_CMD_CRC_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_CMD_CRC_ERR_SIGNAL_EN_TRUE		(1)

#define MSC_CMD_TOUT_ERR_SIGNAL_EN_BIT		BIT(0)
#define MSC_CMD_TOUT_ERR_SIGNAL_EN_FALSE	(0)
#define MSC_CMD_TOUT_ERR_SIGNAL_EN_TRUE	(1)

/* AUTO_CMD_STAT_R */
#define MSC_CMD_NOT_ISSUED_AUTO_CMD12_BIT		BIT(7)
#define MSC_CMD_NOT_ISSUED_AUTO_CMD12_FALSE	(0)
#define MSC_CMD_NOT_ISSUED_AUTO_CMD12_TRUE		(1)

#define MSC_AUTO_CMD_RESP_ERR_BIT			BIT(5)
#define MSC_AUTO_CMD_RESP_ERR_FALSE		(0)
#define MSC_AUTO_CMD_RESP_ERR_TRUE			(1)

#define MSC_AUTO_CMD_IDX_ERR_BIT			BIT(4)
#define MSC_AUTO_CMD_IDX_ERR_FALSE			(0)
#define MSC_AUTO_CMD_IDX_ERR_TRUE			(1)

#define MSC_AUTO_CMD_EBIT_ERR_BIT			BIT(3)
#define MSC_AUTO_CMD_EBIT_ERR_FALSE		(0)
#define MSC_AUTO_CMD_EBIT_ERR_TRUE			(1)

#define MSC_AUTO_CMD_CRC_ERR_BIT			BIT(2)
#define MSC_AUTO_CMD_CRC_ERR_FALSE			(0)
#define MSC_AUTO_CMD_CRC_ERR_TRUE			(1)

#define MSC_AUTO_CMD_TOUT_ERR_BIT			BIT(1)
#define MSC_AUTO_CMD_TOUT_ERR_FALSE		(0)
#define MSC_AUTO_CMD_TOUT_ERR_TRUE			(1)

#define MSC_AUTO_CMD12_NOT_EXEC_BIT		BIT(0)
#define MSC_AUTO_CMD12_NOT_EXEC_FALSE		(0)
#define MSC_AUTO_CMD12_NOT_EXEC_TRUE		(1)

/* HOST_CTRL2_R */
#define MSC_PRESET_VAL_ENABLE_BIT			BIT(15)
#define MSC_PRESET_VAL_ENABLE_FALSE		(0)
#define MSC_PRESET_VAL_ENABLE_TRUE			(1)

#define MSC_ASYNC_INT_ENABLE_BIT			BIT(14)
#define MSC_ASYNC_INT_ENABLE_FALSE			(0)
#define MSC_ASYNC_INT_ENABLE_TRUE			(1)

#define MSC_ADDRESSING_BIT					BIT(13)
#define MSC_ADDRESSING_32				(0)
#define MSC_ADDRESSING_64				(1)

#define MSC_HOST_VER4_ENABLE_BIT			BIT(12)
#define MSC_HOST_VER4_ENABLE_FALSE			(0)
#define MSC_HOST_VER4_ENABLE_TRUE			(1)

#define MSC_CMD23_ENABLE_BIT				BIT(11)
#define MSC_CMD23_ENABLE_FALSE				(0)
#define MSC_CMD23_ENABLE_TRUE				(1)

#define MSC_ADMA2_LEN_MODE_BIT				BIT(10)
#define MSC_ADMA2_LEN_MODE_16			(0)
#define MSC_ADMA2_LEN_MODE_26			(1)

#define MSC_UHS2_IF_ENABLE_BIT				BIT(8)
#define MSC_UHS2_IF_ENABLE_FALSE			(0)
#define MSC_UHS2_IF_ENABLE_TRUE			(1)

#define MSC_SAMPLE_CLK_SEL_BIT				BIT(7)
#define MSC_SAMPLE_CLK_SEL_FALSE			(0)
#define MSC_SAMPLE_CLK_SEL_TRUE			(1)

#define MSC_EXEC_TUNING_BIT				BIT(6)
#define MSC_EXEC_TUNING_FALSE				(0)
#define MSC_EXEC_TUNING_TRUE				(1)

#define MSC_DRV_STRENGTH_SEL_HBIT			(5)
#define MSC_DRV_STRENGTH_SEL_LBIT			(4)
#define MSC_DRV_STRENGTH_SEL_MASK			GENMASK(MSC_DRV_STRENGTH_SEL_HBIT, MSC_DRV_STRENGTH_SEL_LBIT)
#define MSC_DRV_STRENGTH_SEL_TYPEB			(0x0 << MSC_DRV_STRENGTH_SEL_LBIT)
#define MSC_DRV_STRENGTH_SEL_TYPEA			(0x1 << MSC_DRV_STRENGTH_SEL_LBIT)
#define MSC_DRV_STRENGTH_SEL_TYPEC			(0x2 << MSC_DRV_STRENGTH_SEL_LBIT)
#define MSC_DRV_STRENGTH_SEL_TYPED			(0x3 << MSC_DRV_STRENGTH_SEL_LBIT)

#define MSC_SIGNALING_EN_BIT				BIT(3)
#define MSC_SIGNALING_EN_V_3_3				(0)
#define MSC_SIGNALING_EN_V_1_8				(1)

#define MSC_UHS_MODE_SEL_HBIT				(2)
#define MSC_UHS_MODE_SEL_LBIT				(0)
#define MSC_UHS_MODE_SEL_MASK				GENMASK(MSC_UHS_MODE_SEL_HBIT, MSC_UHS_MODE_SEL_LBIT)
#define MSC_UHS_MODE_SEL_SDR12				(0x0 << MSC_UHS_MODE_SEL_LBIT)
#define MSC_UHS_MODE_SEL_SDR25				(0x1 << MSC_UHS_MODE_SEL_LBIT)
#define MSC_UHS_MODE_SEL_SDR50				(0x2 << MSC_UHS_MODE_SEL_LBIT)
#define MSC_UHS_MODE_SEL_SDR104			(0x3 << MSC_UHS_MODE_SEL_LBIT)
#define MSC_UHS_MODE_SEL_DDR50				(0x4 << MSC_UHS_MODE_SEL_LBIT)
#define MSC_UHS_MODE_SEL_RSVD5				(0x5 << MSC_UHS_MODE_SEL_LBIT)
#define MSC_UHS_MODE_SEL_RSVD6				(0x6 << MSC_UHS_MODE_SEL_LBIT)
#define MSC_UHS_MODE_SEL_UHS2				(0x7 << MSC_UHS_MODE_SEL_LBIT)

/* CAPABILITIES1_R */
#define MSC_SLOT_TYPE_R_HBIT				(31)
#define MSC_SLOT_TYPE_R_LBIT				(30)
#define MSC_SLOT_TYPE_R_MASK				GENMASK(MSC_SLOT_TYPE_R_HBIT, MSC_SLOT_TYPE_R_LBIT)
#define MSC_SLOT_TYPE_R_REMOVABLE_SLOT		(0x0 << MSC_SLOT_TYPE_R_LBIT)
#define MSC_SLOT_TYPE_R_EMBEDDED_SLOT		(0x1 << MSC_SLOT_TYPE_R_LBIT)
#define MSC_SLOT_TYPE_R_SHARED_SLOT		(0x2 << MSC_SLOT_TYPE_R_LBIT)
#define MSC_SLOT_TYPE_R_UHS2_EMBEDDED_SLOT	(0x3 << MSC_SLOT_TYPE_R_LBIT)

#define MSC_ASYNC_INT_SUPPORT_BIT			BIT(29)
#define MSC_ASYNC_INT_SUPPORT_FALSE		(0)
#define MSC_ASYNC_INT_SUPPORT_TRUE			(1)

#define MSC_SYS_ADDR_64_V3_BIT				BIT(28)
#define MSC_SYS_ADDR_64_V3_FALSE			(0)
#define MSC_SYS_ADDR_64_V3_TRUE			(1)

#define MSC_SYS_ADDR_64_V4_BIT				BIT(27)
#define MSC_SYS_ADDR_64_V4_FALSE			(0)
#define MSC_SYS_ADDR_64_V4_TRUE			(1)

#define MSC_VOLT_18_BIT					BIT(26)
#define MSC_VOLT_18_FALSE					(0)
#define MSC_VOLT_18_TRUE					(1)

#define MSC_VOLT_30_BIT					BIT(25)
#define MSC_VOLT_30_FALSE					(0)
#define MSC_VOLT_30_TRUE					(1)

#define MSC_VOLT_33_BIT					BIT(24)
#define MSC_VOLT_33_FALSE					(0)
#define MSC_VOLT_33_TRUE					(1)

#define MSC_SUS_RES_SUPPORT_BIT			BIT(23)
#define MSC_SUS_RES_SUPPORT_FALSE			(0)
#define MSC_SUS_RES_SUPPORT_TRUE			(1)

#define MSC_SDMA_SUPPORT_BIT				BIT(22)
#define MSC_SDMA_SUPPORT_FALSE				(0)
#define MSC_SDMA_SUPPORT_TRUE				(1)

#define MSC_HIGH_SPEED_SUPPORT_BIT			BIT(21)
#define MSC_HIGH_SPEED_SUPPORT_FALSE		(0)
#define MSC_HIGH_SPEED_SUPPORT_TRUE		(1)

#define MSC_ADMA2_SUPPORT_BIT				BIT(19)
#define MSC_ADMA2_SUPPORT_FALSE			(0)
#define MSC_ADMA2_SUPPORT_TRUE				(1)

#define MSC_EMBEDDED_8_BIT_BIT				BIT(18)
#define MSC_EMBEDDED_8_BIT_FALSE			(0)
#define MSC_EMBEDDED_8_BIT_TRUE			(1)

#define MSC_MAX_BLK_LEN_HBIT				(17)
#define MSC_MAX_BLK_LEN_LBIT				(16)
#define MSC_MAX_BLK_LEN_MASK				GENMASK(MSC_MAX_BLK_LEN_HBIT, MSC_MAX_BLK_LEN_LBIT)
#define MSC_MAX_BLK_LEN_ZERO				(0x0 << MSC_MAX_BLK_LEN_LBIT)
#define MSC_MAX_BLK_LEN_ONE				(0x1 << MSC_MAX_BLK_LEN_LBIT)
#define MSC_MAX_BLK_LEN_TWO				(0x2 << MSC_MAX_BLK_LEN_LBIT)
#define MSC_MAX_BLK_LEN_THREE				(0x3 << MSC_MAX_BLK_LEN_LBIT)

#define MSC_BASE_CLK_FREQ_HBIT				(15)
#define MSC_BASE_CLK_FREQ_LBIT				(8)
#define MSC_BASE_CLK_FREQ_MASK				GENMASK(MSC_BASE_CLK_FREQ_HBIT, MSC_BASE_CLK_FREQ_LBIT)

#define MSC_TOUT_CLK_UNIT_BIT				BIT(7)
#define MSC_TOUT_CLK_UNIT_KHZ				(0)
#define MSC_TOUT_CLK_UNIT_MHZ				(1)

#define MSC_TOUT_CLK_FREQ_HBIT				(5)
#define MSC_TOUT_CLK_FREQ_LBIT				(0)
#define MSC_TOUT_CLK_FREQ_MASK				GENMASK(MSC_TOUT_CLK_FREQ_HBIT, MSC_TOUT_CLK_FREQ_LBIT)

/* CAPABILITIES1_R */
#define MSC_VDD2_18V_SUPPORT_BIT			BIT(28)
#define MSC_VDD2_18V_SUPPORT_FALSE			(0)
#define MSC_VDD2_18V_SUPPORT_TRUE			(1)

#define MSC_ADMA3_SUPPORT_BIT				BIT(27)
#define MSC_ADMA3_SUPPORT_FALSE			(0)
#define MSC_ADMA3_SUPPORT_TRUE				(1)

#define MSC_CLK_MUL_HBIT					(23)
#define MSC_CLK_MUL_LBIT					(16)
#define MSC_CLK_MUL_MASK					GENMASK(MSC_CLK_MUL_HBIT, MSC_CLK_MUL_LBIT)

#define MSC_RE_TUNING_MODES_HBIT			(15)
#define MSC_RE_TUNING_MODES_LBIT			(14)
#define MSC_RE_TUNING_MODES_MASK			GENMASK(MSC_RE_TUNING_MODES_HBIT, MSC_RE_TUNING_MODES_LBIT)
#define MSC_RE_TUNING_MODES_MODE1			(0x0 << MSC_RE_TUNING_MODES_LBIT)
#define MSC_RE_TUNING_MODES_MODE2			(0x1 << MSC_RE_TUNING_MODES_LBIT)
#define MSC_RE_TUNING_MODES_MODE3			(0x2 << MSC_RE_TUNING_MODES_LBIT)
#define MSC_RE_TUNING_MODES_RSVD_MODE		(0x3 << MSC_RE_TUNING_MODES_LBIT)

#define MSC_USE_TUNING_SDR50_BIT			BIT(13)
#define MSC_USE_TUNING_SDR50_ZERO			(0)
#define MSC_USE_TUNING_SDR50_ONE			(1)

#define MSC_RETUNE_CNT_HBIT				(11)
#define MSC_RETUNE_CNT_LBIT				(8)
#define MSC_RETUNE_CNT_MASK				GENMASK(RETUNE_CNT_HBIT, RETUNE_CNT_LBIT)

#define MSC_DRV_TYPED_BIT					BIT(6)
#define MSC_DRV_TYPED_FALSE				(0)
#define MSC_DRV_TYPED_TRUE					(1)

#define MSC_DRV_TYPEC_BIT					BIT(5)
#define MSC_DRV_TYPEC_FALSE				(0)
#define MSC_DRV_TYPEC_TRUE					(1)

#define MSC_DRV_TYPEA_BIT					BIT(4)
#define MSC_DRV_TYPEA_FALSE				(0)
#define MSC_DRV_TYPEA_TRUE					(1)

#define MSC_UHS2_SUPPORT_BIT				BIT(3)
#define MSC_UHS2_SUPPORT_FALSE				(0)
#define MSC_UHS2_SUPPORT_TRUE				(1)

#define MSC_DDR50_SUPPORT_BIT				BIT(2)
#define MSC_DDR50_SUPPORT_FALSE			(0)
#define MSC_DDR50_SUPPORT_TRUE				(1)

#define MSC_SDR104_SUPPORT_BIT				BIT(1)
#define MSC_SDR104_SUPPORT_FALSE			(0)
#define MSC_SDR104_SUPPORT_TRUE			(1)

#define MSC_SDR50_SUPPORT_BIT				BIT(0)
#define MSC_SDR50_SUPPORT_FALSE			(0)
#define MSC_SDR50_SUPPORT_TRUE				(1)

/* CURR_CAPABILITIES1_R */
#define MSC_MAX_CUR_18V_HBIT				(23)
#define MSC_MAX_CUR_18V_LBIT				(16)
#define MSC_MAX_CUR_18V_MASK				GENMASK(MSC_MAX_CUR_18V_HBIT, MSC_MAX_CUR_18V_LBIT)

#define MSC_MAX_CUR_30V_HBIT				(15)
#define MSC_MAX_CUR_30V_LBIT				(8)
#define MSC_MAX_CUR_30V_MASK				GENMASK(MSC_MAX_CUR_30V_HBIT, MSC_MAX_CUR_30V_LBIT)

#define MSC_MAX_CUR_33V_HBIT				(7)
#define MSC_MAX_CUR_33V_LBIT				(0)
#define MSC_MAX_CUR_33V_MASK				GENMASK(MSC_MAX_CUR_33V_HBIT, MSC_MAX_CUR_33V_LBIT)

/* CURR_CAPABILITIES2_R */
#define MSC_MAX_CUR_VDD2_18V_HBIT			(7)
#define MSC_MAX_CUR_VDD2_18V_LBIT			(0)
#define MSC_MAX_CUR_VDD2_18V_MASK			GENMASK(MSC_MAX_CUR_VDD2_18V_HBIT, MSC_MAX_CUR_VDD2_18V_LBIT)

/* FORCE_AUTO_CMD_STAT_R */
#define MSC_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_BIT		BIT(7)
#define MSC_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_FALSE		(0)
#define MSC_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_TRUE		(1)

#define MSC_FORCE_AUTO_CMD_RESP_ERR_BIT				BIT(5)
#define MSC_FORCE_AUTO_CMD_RESP_ERR_FALSE				(0)
#define MSC_FORCE_AUTO_CMD_RESP_ERR_TRUE				(1)

#define MSC_FORCE_AUTO_CMD_IDX_ERR_BIT					BIT(4)
#define MSC_FORCE_AUTO_CMD_IDX_ERR_FALSE				(0)
#define MSC_FORCE_AUTO_CMD_IDX_ERR_TRUE				(1)

#define MSC_FORCE_AUTO_CMD_EBIT_ERR_BIT				BIT(3)
#define MSC_FORCE_AUTO_CMD_EBIT_ERR_FALSE				(0)
#define MSC_FORCE_AUTO_CMD_EBIT_ERR_TRUE				(1)

#define MSC_FORCE_AUTO_CMD_CRC_ERR_BIT					BIT(2)
#define MSC_FORCE_AUTO_CMD_CRC_ERR_FALSE				(0)
#define MSC_FORCE_AUTO_CMD_CRC_ERR_TRUE				(1)

#define MSC_FORCE_AUTO_CMD_TOUT_ERR_BIT				BIT(1)
#define MSC_FORCE_AUTO_CMD_TOUT_ERR_FALSE				(0)
#define MSC_FORCE_AUTO_CMD_TOUT_ERR_TRUE				(1)

#define MSC_FORCE_AUTO_CMD12_NOT_EXEC_BIT				BIT(0)
#define MSC_FORCE_AUTO_CMD12_NOT_EXEC_FALSE			(0)
#define MSC_FORCE_AUTO_CMD12_NOT_EXEC_TRUE				(1)

/* FORCE_ERROR_INT_STAT_R */
#define	MSC_FORCE_VENDOR_ERR3_BIT			BIT(15)
#define	MSC_FORCE_VENDOR_ERR3_FALSE		(0)
#define	MSC_FORCE_VENDOR_ERR3_TRUE			(1)

#define	MSC_FORCE_VENDOR_ERR2_BIT			BIT(14)
#define	MSC_FORCE_VENDOR_ERR2_FALSE		(0)
#define	MSC_FORCE_VENDOR_ERR2_TRUE			(1)

#define	MSC_FORCE_VENDOR_ERR1_BIT			BIT(13)
#define	MSC_FORCE_VENDOR_ERR1_FALSE		(0)
#define	MSC_FORCE_VENDOR_ERR1_TRUE			(1)

#define	MSC_FORCE_BOOT_ACK_ERR_BIT			BIT(12)
#define	MSC_FORCE_BOOT_ACK_ERR_FALSE		(0)
#define	MSC_FORCE_BOOT_ACK_ERR_TRUE		(1)

#define	MSC_FORCE_RESP_ERR_BIT				BIT(11)
#define	MSC_FORCE_RESP_ERR_FALSE			(0)
#define	MSC_FORCE_RESP_ERR_TRUE			(1)

#define	MSC_FORCE_TUNING_ERR_BIT			BIT(10)
#define	MSC_FORCE_TUNING_ERR_FALSE			(0)
#define	MSC_FORCE_TUNING_ERR_TRUE			(1)

#define	MSC_FORCE_ADMA_ERR_BIT				BIT(9)
#define	MSC_FORCE_ADMA_ERR_FALSE			(0)
#define	MSC_FORCE_ADMA_ERR_TRUE			(1)

#define	MSC_FORCE_AUTO_CMD_ERR_BIT			BIT(8)
#define	MSC_FORCE_AUTO_CMD_ERR_FALSE		(0)
#define	MSC_FORCE_AUTO_CMD_ERR_TRUE		(1)

#define	MSC_FORCE_CUR_LMT_ERR_BIT			BIT(7)
#define	MSC_FORCE_CUR_LMT_ERR_FALSE		(0)
#define	MSC_FORCE_CUR_LMT_ERR_TRUE			(1)

#define	MSC_FORCE_DATA_END_BIT_ERR_BIT		BIT(6)
#define	MSC_FORCE_DATA_END_BIT_ERR_FALSE	(0)
#define	MSC_FORCE_DATA_END_BIT_ERR_TRUE	(1)

#define	MSC_FORCE_DATA_CRC_ERR_BIT			BIT(5)
#define	MSC_FORCE_DATA_CRC_ERR_FALSE		(0)
#define	MSC_FORCE_DATA_CRC_ERR_TRUE		(1)

#define	MSC_FORCE_DATA_TOUT_ERR_BIT		BIT(4)
#define	MSC_FORCE_DATA_TOUT_ERR_FALSE		(0)
#define	MSC_FORCE_DATA_TOUT_ERR_TRUE		(1)

#define	MSC_FORCE_CMD_IDX_ERR_BIT			BIT(3)
#define	MSC_FORCE_CMD_IDX_ERR_FALSE		(0)
#define	MSC_FORCE_CMD_IDX_ERR_TRUE			(1)

#define	MSC_FORCE_CMD_END_BIT_ERR_BIT		BIT(2)
#define	MSC_FORCE_CMD_END_BIT_ERR_FALSE	(0)
#define	MSC_FORCE_CMD_END_BIT_ERR_TRUE		(1)

#define	MSC_FORCE_CMD_CRC_ERR_BIT			BIT(1)
#define	MSC_FORCE_CMD_CRC_ERR_FALSE		(0)
#define	MSC_FORCE_CMD_CRC_ERR_TRUE			(1)

#define	MSC_FORCE_CMD_TOUT_ERR_BIT			BIT(0)
#define	MSC_FORCE_CMD_TOUT_ERR_FALSE		(0)
#define	MSC_FORCE_CMD_TOUT_ERR_TRUE		(1)

/* ADMA_ERR_STAT_R */
#define MSC_ADMA_LEN_ERR_BIT				BIT(2)
#define MSC_ADMA_LEN_ERR_NO_ERR			(0)
#define MSC_ADMA_LEN_ERR_ERROR				(1)

#define MSC_ADMA_ERR_STATES_HBIT			(1)
#define MSC_ADMA_ERR_STATES_LBIT			(0)
#define MSC_ADMA_ERR_STATES_MASK			GENMASK(MSC_ADMA_ERR_STATES_HBIT, MSC_ADMA_ERR_STATES_LBIT)
#define MSC_ADMA_ERR_STATES_STOP			(0x0 << MSC_ADMA_ERR_STATES_HBIT)
#define MSC_ADMA_ERR_STATES_FDS			(0x1 << MSC_ADMA_ERR_STATES_HBIT)
#define MSC_ADMA_ERR_STATES_UNUSED			(0x2 << MSC_ADMA_ERR_STATES_HBIT)
#define MSC_ADMA_ERR_STATES_TFR			(0x3 << MSC_ADMA_ERR_STATES_HBIT)

/* PRESET_INIT_R */
#define MSC_INIT_DRV_SEL_VAL_HBIT			(15)
#define MSC_INIT_DRV_SEL_VAL_LBIT			(14)
#define MSC_INIT_DRV_SEL_VAL_MASK			GENMASK(MSC_INIT_DRV_SEL_VAL_HBIT, MSC_INIT_DRV_SEL_VAL_LBIT)
#define MSC_INIT_DRV_SEL_VAL_TYPEB			(0x0 << MSC_INIT_DRV_SEL_VAL_LBIT)
#define MSC_INIT_DRV_SEL_VAL_TYPEA			(0x1 << MSC_INIT_DRV_SEL_VAL_LBIT)
#define MSC_INIT_DRV_SEL_VAL_TYPEC			(0x2 << MSC_INIT_DRV_SEL_VAL_LBIT)
#define MSC_INIT_DRV_SEL_VAL_TYPED			(0x3 << MSC_INIT_DRV_SEL_VAL_LBIT)

#define MSC_INIT_CLK_GEN_SEL_VAL_BIT		BIT(10)
#define MSC_INIT_CLK_GEN_SEL_VAL_FALSE		(0)
#define MSC_INIT_CLK_GEN_SEL_VAL_PROG		(1)

#define MSC_INIT_FREQ_SEL_VAL_HBIT			(9)
#define MSC_INIT_FREQ_SEL_VAL_LBIT			(0)
#define MSC_INIT_FREQ_SEL_VAL_MASK			GENMASK(MSC_INIT_FREQ_SEL_VAL_HBIT, MSC_INIT_FREQ_SEL_VAL_LBIT)

/* PRESET_DS_R */
#define MSC_DS_DRV_SEL_VAL_HBIT			(15)
#define MSC_DS_DRV_SEL_VAL_LBIT			(14)
#define MSC_DS_DRV_SEL_VAL_MASK			GENMASK(MSC_DS_DRV_SEL_VAL_HBIT, MSC_DS_DRV_SEL_VAL_LBIT)
#define MSC_DS_DRV_SEL_VAL_TYPEB			(0x0 << MSC_DS_DRV_SEL_VAL_LBIT)
#define MSC_DS_DRV_SEL_VAL_TYPEA			(0x1 << MSC_DS_DRV_SEL_VAL_LBIT)
#define MSC_DS_DRV_SEL_VAL_TYPEC			(0x2 << MSC_DS_DRV_SEL_VAL_LBIT)
#define MSC_DS_DRV_SEL_VAL_TYPED			(0x3 << MSC_DS_DRV_SEL_VAL_LBIT)

#define MSC_DS_CLK_GEN_SEL_VAL_BIT			BIT(10)
#define MSC_DS_CLK_GEN_SEL_VAL_FALSE		(0)
#define MSC_DS_CLK_GEN_SEL_VAL_PROG		(1)

#define MSC_DS_FREQ_SEL_VAL_HBIT			(9)
#define MSC_DS_FREQ_SEL_VAL_LBIT			(0)
#define MSC_DS_FREQ_SEL_VAL_MASK			GENMASK(MSC_DS_FREQ_SEL_VAL_HBIT, MSC_DS_FREQ_SEL_VAL_LBIT)

/* PRESET_HS_R */
#define MSC_HS_DRV_SEL_VAL_HBIT			(15)
#define MSC_HS_DRV_SEL_VAL_LBIT			(14)
#define MSC_HS_DRV_SEL_VAL_MASK			GENMASK(MSC_HS_DRV_SEL_VAL_HBIT, MSC_HS_DRV_SEL_VAL_LBIT)
#define MSC_HS_DRV_SEL_VAL_TYPEB			(0x0 << MSC_HS_DRV_SEL_VAL_LBIT)
#define MSC_HS_DRV_SEL_VAL_TYPEA			(0x1 << MSC_HS_DRV_SEL_VAL_LBIT)
#define MSC_HS_DRV_SEL_VAL_TYPEC			(0x2 << MSC_HS_DRV_SEL_VAL_LBIT)
#define MSC_HS_DRV_SEL_VAL_TYPED			(0x3 << MSC_HS_DRV_SEL_VAL_LBIT)

#define MSC_HS_CLK_GEN_SEL_VAL_BIT			BIT(10)
#define MSC_HS_CLK_GEN_SEL_VAL_FALSE		(0)
#define MSC_HS_CLK_GEN_SEL_VAL_PROG		(1)

#define MSC_HS_FREQ_SEL_VAL_HBIT			(9)
#define MSC_HS_FREQ_SEL_VAL_LBIT			(0)
#define MSC_HS_FREQ_SEL_VAL_MASK			GENMASK(MSC_HS_FREQ_SEL_VAL_HBIT, MSC_HS_FREQ_SEL_VAL_LBIT)

/* PRESET_SDR12_R */
#define MSC_SDR12_DRV_SEL_VAL_HBIT			(15)
#define MSC_SDR12_DRV_SEL_VAL_LBIT			(14)
#define MSC_SDR12_DRV_SEL_VAL_MASK			GENMASK(MSC_SDR12_DRV_SEL_VAL_HBIT, MSC_SDR12_DRV_SEL_VAL_LBIT)
#define MSC_SDR12_DRV_SEL_VAL_TYPEB		(0x0 << MSC_SDR12_DRV_SEL_VAL_LBIT)
#define MSC_SDR12_DRV_SEL_VAL_TYPEA		(0x1 << MSC_SDR12_DRV_SEL_VAL_LBIT)
#define MSC_SDR12_DRV_SEL_VAL_TYPEC		(0x2 << MSC_SDR12_DRV_SEL_VAL_LBIT)
#define MSC_SDR12_DRV_SEL_VAL_TYPED		(0x3 << MSC_SDR12_DRV_SEL_VAL_LBIT)

#define MSC_SDR12_CLK_GEN_SEL_VAL_BIT		BIT(10)
#define MSC_SDR12_CLK_GEN_SEL_VAL_FALSE	(0)
#define MSC_SDR12_CLK_GEN_SEL_VAL_PROG		(1)

#define MSC_SDR12_FREQ_SEL_VAL_HBIT		(9)
#define MSC_SDR12_FREQ_SEL_VAL_LBIT		(0)
#define MSC_SDR12_FREQ_SEL_VAL_MASK		GENMASK(MSC_SDR12_FREQ_SEL_VAL_HBIT, MSC_SDR12_FREQ_SEL_VAL_LBIT)

/* PRESET_SDR25_R */
#define MSC_SDR25_DRV_SEL_VAL_HBIT			(15)
#define MSC_SDR25_DRV_SEL_VAL_LBIT			(14)
#define MSC_SDR25_DRV_SEL_VAL_MASK			GENMASK(MSC_SDR25_DRV_SEL_VAL_HBIT, MSC_SDR25_DRV_SEL_VAL_LBIT)
#define MSC_SDR25_DRV_SEL_VAL_TYPEB		(0x0 << MSC_SDR25_DRV_SEL_VAL_LBIT)
#define MSC_SDR25_DRV_SEL_VAL_TYPEA		(0x1 << MSC_SDR25_DRV_SEL_VAL_LBIT)
#define MSC_SDR25_DRV_SEL_VAL_TYPEC		(0x2 << MSC_SDR25_DRV_SEL_VAL_LBIT)
#define MSC_SDR25_DRV_SEL_VAL_TYPED		(0x3 << MSC_SDR25_DRV_SEL_VAL_LBIT)

#define MSC_SDR25_CLK_GEN_SEL_VAL_BIT		BIT(10)
#define MSC_SDR25_CLK_GEN_SEL_VAL_FALSE	(0)
#define MSC_SDR25_CLK_GEN_SEL_VAL_PROG		(1)

#define MSC_SDR25_FREQ_SEL_VAL_HBIT		(9)
#define MSC_SDR25_FREQ_SEL_VAL_LBIT		(0)
#define MSC_SDR25_FREQ_SEL_VAL_MASK		GENMASK(MSC_SDR25_FREQ_SEL_VAL_HBIT, MSC_SDR25_FREQ_SEL_VAL_LBIT)

/* PRESET_SDR50_R */
#define MSC_SDR50_DRV_SEL_VAL_HBIT			(15)
#define MSC_SDR50_DRV_SEL_VAL_LBIT			(14)
#define MSC_SDR50_DRV_SEL_VAL_MASK			GENMASK(MSC_SDR50_DRV_SEL_VAL_HBIT, MSC_SDR50_DRV_SEL_VAL_LBIT)
#define MSC_SDR50_DRV_SEL_VAL_TYPEB		(0x0 << MSC_SDR50_DRV_SEL_VAL_LBIT)
#define MSC_SDR50_DRV_SEL_VAL_TYPEA		(0x1 << MSC_SDR50_DRV_SEL_VAL_LBIT)
#define MSC_SDR50_DRV_SEL_VAL_TYPEC		(0x2 << MSC_SDR50_DRV_SEL_VAL_LBIT)
#define MSC_SDR50_DRV_SEL_VAL_TYPED		(0x3 << MSC_SDR50_DRV_SEL_VAL_LBIT)

#define MSC_SDR50_CLK_GEN_SEL_VAL_BIT		BIT(10)
#define MSC_SDR50_CLK_GEN_SEL_VAL_FALSE	(0)
#define MSC_SDR50_CLK_GEN_SEL_VAL_PROG		(1)

#define MSC_SDR50_FREQ_SEL_VAL_HBIT		(9)
#define MSC_SDR50_FREQ_SEL_VAL_LBIT		(0)
#define MSC_SDR50_FREQ_SEL_VAL_MASK		GENMASK(MSC_SDR50_FREQ_SEL_VAL_HBIT, MSC_SDR50_FREQ_SEL_VAL_LBIT)

/* PRESET_SDR104_R */
#define MSC_SDR104_DRV_SEL_VAL_HBIT		(15)
#define MSC_SDR104_DRV_SEL_VAL_LBIT		(14)
#define MSC_SDR104_DRV_SEL_VAL_MASK		GENMASK(MSC_SDR104_DRV_SEL_VAL_HBIT, MSC_SDR104_DRV_SEL_VAL_LBIT)
#define MSC_SDR104_DRV_SEL_VAL_TYPEB		(0x0 << MSC_SDR104_DRV_SEL_VAL_LBIT)
#define MSC_SDR104_DRV_SEL_VAL_TYPEA		(0x1 << MSC_SDR104_DRV_SEL_VAL_LBIT)
#define MSC_SDR104_DRV_SEL_VAL_TYPEC		(0x2 << MSC_SDR104_DRV_SEL_VAL_LBIT)
#define MSC_SDR104_DRV_SEL_VAL_TYPED		(0x3 << MSC_SDR104_DRV_SEL_VAL_LBIT)

#define MSC_SDR104_CLK_GEN_SEL_VAL_BIT		BIT(10)
#define MSC_SDR104_CLK_GEN_SEL_VAL_FALSE	(0)
#define MSC_SDR104_CLK_GEN_SEL_VAL_PROG	(1)

#define MSC_SDR104_FREQ_SEL_VAL_HBIT		(9)
#define MSC_SDR104_FREQ_SEL_VAL_LBIT		(0)
#define MSC_SDR104_FREQ_SEL_VAL_MASK		GENMASK(MSC_SDR104_FREQ_SEL_VAL_HBIT, MSC_SDR104_FREQ_SEL_VAL_LBIT)

/* PRESET_DDR50_R */
#define MSC_DDR50_DRV_SEL_VAL_HBIT			(15)
#define MSC_DDR50_DRV_SEL_VAL_LBIT			(14)
#define MSC_DDR50_DRV_SEL_VAL_MASK			GENMASK(MSC_DDR50_DRV_SEL_VAL_HBIT, MSC_DDR50_DRV_SEL_VAL_LBIT)
#define MSC_DDR50_DRV_SEL_VAL_TYPEB		(0x0 << MSC_DDR50_DRV_SEL_VAL_LBIT)
#define MSC_DDR50_DRV_SEL_VAL_TYPEA		(0x1 << MSC_DDR50_DRV_SEL_VAL_LBIT)
#define MSC_DDR50_DRV_SEL_VAL_TYPEC		(0x2 << MSC_DDR50_DRV_SEL_VAL_LBIT)
#define MSC_DDR50_DRV_SEL_VAL_TYPED		(0x3 << MSC_DDR50_DRV_SEL_VAL_LBIT)

#define MSC_DDR50_CLK_GEN_SEL_VAL_BIT		BIT(10)
#define MSC_DDR50_CLK_GEN_SEL_VAL_FALSE	(0)
#define MSC_DDR50_CLK_GEN_SEL_VAL_PROG		(1)

#define MSC_DDR50_FREQ_SEL_VAL_HBIT		(9)
#define MSC_DDR50_FREQ_SEL_VAL_LBIT		(0)
#define MSC_DDR50_FREQ_SEL_VAL_MASK		GENMASK(MSC_DDR50_FREQ_SEL_VAL_HBIT, MSC_DDR50_FREQ_SEL_VAL_LBIT)

/* P_EMBEDDED_CNTRL */
#define MSC_EMBEDDED_CNTRL_REG_OFFSET_ADDR_HBIT			(11)
#define MSC_EMBEDDED_CNTRL_REG_OFFSET_ADDR_LBIT			(0)
#define MSC_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK			\
	GENMASK(MSC_EMBEDDED_CNTRL_REG_OFFSET_ADDR_HBIT, MSC_EMBEDDED_CNTRL_REG_OFFSET_ADDR_LBIT)

/* P_VENDOR_SPECIFIC_AREA */
#define MSC_VENDOR_SPECIFIC_REG_OFFSET_ADDR_HBIT		(11)
#define MSC_VENDOR_SPECIFIC_REG_OFFSET_ADDR_LBIT		(0)
#define MSC_VENDOR_SPECIFIC_REG_OFFSET_ADDR_MASK		\
	GENMASK(MSC_VENDOR_SPECIFIC_REG_OFFSET_ADDR_HBIT, MSC_VENDOR_SPECIFIC_REG_OFFSET_ADDR_LBIT)

/* P_VENDOR2_SPECIFIC_AREA */
#define MSC_CQE_REG_OFFSET_ADDR_HBIT		(11)
#define MSC_CQE_REG_OFFSET_ADDR_LBIT		(0)
#define MSC_CQE_REG_OFFSET_ADDR_MASK		\
	GENMASK(MSC_CQE_REG_OFFSET_ADDR_HBIT, MSC_CQE_REG_OFFSET_ADDR_LBIT)

/* SLOT_INTR_STATUS_R */
#define MSC_INTR_SLOT_HBIT					(7)
#define MSC_INTR_SLOT_LBIT					(0)
#define MSC_INTR_SLOT_MASK					GENMASK(MSC_INTR_SLOT_HBIT, MSC_INTR_SLOT_LBIT)

/* HOST_CNTRL_VERS_R */
#define MSC_VENDOR_VERSION_NUM_HBIT		(15)
#define MSC_VENDOR_VERSION_NUM_LBIT		(8)
#define MSC_VENDOR_VERSION_NUM_MASK		GENMASK(MSC_VENDOR_VERSION_NUM_HBIT, MSC_VENDOR_VERSION_NUM_LBIT)

#define MSC_SPEC_VERSION_NUM_HBIT			(7)
#define MSC_SPEC_VERSION_NUM_LBIT			(0)
#define MSC_SPEC_VERSION_NUM_MASK			GENMASK(MSC_SPEC_VERSION_NUM_HBIT, MSC_SPEC_VERSION_NUM_LBIT)
#define MSC_SPEC_VERSION_NUM_1_0_0			(0x0 << MSC_SPEC_VERSION_NUM_LBIT)
#define MSC_SPEC_VERSION_NUM_2_0_0			(0x1 << MSC_SPEC_VERSION_NUM_LBIT)
#define MSC_SPEC_VERSION_NUM_3_0_0			(0x2 << MSC_SPEC_VERSION_NUM_LBIT)
#define MSC_SPEC_VERSION_NUM_4_0_0			(0x3 << MSC_SPEC_VERSION_NUM_LBIT)
#define MSC_SPEC_VERSION_NUM_4_1_0			(0x4 << MSC_SPEC_VERSION_NUM_LBIT)
#define MSC_SPEC_VERSION_NUM_4_2_0			(0x5 << MSC_SPEC_VERSION_NUM_LBIT)

/* EMBEDDED_CTRL_R */
#define MSC_BACK_END_PWR_CTRL_HBIT			(30)
#define MSC_BACK_END_PWR_CTRL_LBIT			(24)
#define MSC_BACK_END_PWR_CTRL_MASK			GENMASK(MSC_BACK_END_PWR_CTRL_HBIT, MSC_BACK_END_PWR_CTRL_LBIT)
#define MSC_BACK_END_PWR_CTRL_DEV1			(0x1 << MSC_BACK_END_PWR_CTRL_LBIT)
#define MSC_BACK_END_PWR_CTRL_DEV2			(0x1 << (MSC_BACK_END_PWR_CTRL_LBIT + 1))
#define MSC_BACK_END_PWR_CTRL_DEV3			(0x1 << (MSC_BACK_END_PWR_CTRL_LBIT + 2))
#define MSC_BACK_END_PWR_CTRL_DEV4			(0x1 << (MSC_BACK_END_PWR_CTRL_LBIT + 3))
#define MSC_BACK_END_PWR_CTRL_DEV5			(0x1 << (MSC_BACK_END_PWR_CTRL_LBIT + 4))
#define MSC_BACK_END_PWR_CTRL_DEV6			(0x1 << (MSC_BACK_END_PWR_CTRL_LBIT + 5))
#define MSC_BACK_END_PWR_CTRL_DEV7			(0x1 << (MSC_BACK_END_PWR_CTRL_LBIT + 6))
#define MSC_BACK_END_PWR_CTRL_POWER_OFF	(0)
#define MSC_BACK_END_PWR_CTRL_POWER_SUP	(1)

#define MSC_INT_PIN_SEL_HBIT				(22)
#define MSC_INT_PIN_SEL_LBIT				(20)
#define MSC_INT_PIN_SEL_MASK				GENMASK(MSC_INT_PIN_SEL_HBIT, MSC_INT_PIN_SEL_LBIT)
#define MSC_INT_PIN_SEL_INT_DISABLE		(0x0 << MSC_INT_PIN_SEL_LBIT)
#define MSC_INT_PIN_SEL_INT_A				(0x1 << MSC_INT_PIN_SEL_LBIT)
#define MSC_INT_PIN_SEL_INT_B				(0x1 << (MSC_INT_PIN_SEL_LBIT + 1))
#define MSC_INT_PIN_SEL_INT_C				(0x1 << (MSC_INT_PIN_SEL_LBIT + 2))

#define MSC_CLK_PIN_SEL_HBIT				(18)
#define MSC_CLK_PIN_SEL_LBIT				(16)
#define MSC_CLK_PIN_SEL_MASK				GENMASK(MSC_CLK_PIN_SEL_HBIT, MSC_CLK_PIN_SEL_LBIT)
#define MSC_CLK_PIN_SEL_CLK_DISABLE		(0x0 << MSC_CLK_PIN_SEL_LBIT)
#define MSC_CLK_PIN_SEL_CLK1				(0x1 << MSC_CLK_PIN_SEL_LBIT)
#define MSC_CLK_PIN_SEL_CLK2				(0x2 << MSC_CLK_PIN_SEL_LBIT)
#define MSC_CLK_PIN_SEL_CLK3				(0x3 << MSC_CLK_PIN_SEL_LBIT)
#define MSC_CLK_PIN_SEL_CLK4				(0x4 << MSC_CLK_PIN_SEL_LBIT)
#define MSC_CLK_PIN_SEL_CLK5				(0x5 << MSC_CLK_PIN_SEL_LBIT)
#define MSC_CLK_PIN_SEL_CLK6				(0x6 << MSC_CLK_PIN_SEL_LBIT)
#define MSC_CLK_PIN_SEL_CLK7				(0x7 << MSC_CLK_PIN_SEL_LBIT)

#define MSC_BUS_WIDTH_PRESET_HBIT			(14)
#define MSC_BUS_WIDTH_PRESET_LBIT			(8)
#define MSC_BUS_WIDTH_PRESET_MASK			GENMASK(MSC_BUS_WIDTH_PRESET_HBIT, MSC_BUS_WIDTH_PRESET_LBIT)
#define MSC_BUS_WIDTH_PRESET_DEV1			(0x1 << MSC_BUS_WIDTH_PRESET_LBIT)
#define MSC_BUS_WIDTH_PRESET_DEV2			(0x1 << (MSC_BUS_WIDTH_PRESET_LBIT + 1))
#define MSC_BUS_WIDTH_PRESET_DEV3			(0x1 << (MSC_BUS_WIDTH_PRESET_LBIT + 2))
#define MSC_BUS_WIDTH_PRESET_DEV4			(0x1 << (MSC_BUS_WIDTH_PRESET_LBIT + 3))
#define MSC_BUS_WIDTH_PRESET_DEV5			(0x1 << (MSC_BUS_WIDTH_PRESET_LBIT + 4))
#define MSC_BUS_WIDTH_PRESET_DEV6			(0x1 << (MSC_BUS_WIDTH_PRESET_LBIT + 5))
#define MSC_BUS_WIDTH_PRESET_DEV7			(0x1 << (MSC_BUS_WIDTH_PRESET_LBIT + 6))
#define MSC_BUS_WIDTH_PRESET_4				(0)
#define MSC_BUS_WIDTH_PRESET_8				(1)

#define MSC_NUM_INT_PIN_HBIT				(5)
#define MSC_NUM_INT_PIN_LBIT				(4)
#define MSC_NUM_INT_PIN_MASK				GENMASK(MSC_NUM_INT_PIN_HBIT, MSC_NUM_INT_PIN_LBIT)
#define MSC_NUM_INT_PIN_NOT_SUPPORT		(0x0 << MSC_NUM_INT_PIN_LBIT)
#define MSC_NUM_INT_PIN_INT_A				(0x1 << MSC_NUM_INT_PIN_LBIT)
#define MSC_NUM_INT_PIN_INT_A_B			(0x2 << MSC_NUM_INT_PIN_LBIT)
#define MSC_NUM_INT_PIN_INT_A_B_C			(0x3 << MSC_NUM_INT_PIN_LBIT)

#define MSC_NUM_CLK_PIN_HBIT				(2)
#define MSC_NUM_CLK_PIN_LBIT				(0)
#define MSC_NUM_CLK_PIN_MASK				GENMASK(MSC_NUM_CLK_PIN_HBIT, MSC_NUM_CLK_PIN_LBIT)
#define MSC_NUM_CLK_PIN_NOT_SUPPORT		(0x0 << MSC_NUM_CLK_PIN_LBIT)
#define MSC_NUM_CLK_PIN_1_SDCLK			(0x1 << MSC_NUM_CLK_PIN_LBIT)
#define MSC_NUM_CLK_PIN_2_SDCLK			(0x2 << MSC_NUM_CLK_PIN_LBIT)
#define MSC_NUM_CLK_PIN_3_SDCLK			(0x3 << MSC_NUM_CLK_PIN_LBIT)
#define MSC_NUM_CLK_PIN_4_SDCLK			(0x4 << MSC_NUM_CLK_PIN_LBIT)
#define MSC_NUM_CLK_PIN_5_SDCLK			(0x5 << MSC_NUM_CLK_PIN_LBIT)
#define MSC_NUM_CLK_PIN_6_SDCLK			(0x6 << MSC_NUM_CLK_PIN_LBIT)
#define MSC_NUM_CLK_PIN_7_SDCLK			(0x7 << MSC_NUM_CLK_PIN_LBIT)

/* CQVER */
#define MSC_EMMC_VER_MAJOR_HBIT			(11)
#define MSC_EMMC_VER_MAJOR_LBIT			(8)
#define MSC_EMMC_VER_MAJOR_MASK			GENMASK(MSC_EMMC_VER_MAJOR_HBIT, MSC_EMMC_VER_MAJOR_LBIT)

#define MSC_EMMC_VER_MINOR_HBIT			(7)
#define MSC_EMMC_VER_MINOR_LBIT			(4)
#define MSC_EMMC_VER_MINOR_MASK			GENMASK(MSC_EMMC_VER_MINOR_HBIT, MSC_EMMC_VER_MINOR_LBIT)

#define MSC_EMMC_VER_SUFFIX_HBIT			(3)
#define MSC_EMMC_VER_SUFFIX_LBIT			(0)
#define MSC_EMMC_VER_SUFFIX_MASK			GENMASK(MSC_EMMC_VER_SUFFIX_HBIT, MSC_EMMC_VER_SUFFIX_LBIT)

/* CQCAP */
#define MSC_ITCFMUL_HBIT					(15)
#define MSC_ITCFMUL_LBIT					(12)
#define MSC_ITCFMUL_MASK					GENMASK(MSC_ITCFMUL_HBIT, MSC_ITCFMUL_LBIT)
#define MSC_ITCFMUL_1KHZ					(0x0 << MSC_ITCFMUL_LBIT)
#define MSC_ITCFMUL_10KHZ					(0x1 << MSC_ITCFMUL_LBIT)
#define MSC_ITCFMUL_100KHZ					(0x2 << MSC_ITCFMUL_LBIT)
#define MSC_ITCFMUL_1MHZ					(0x3 << MSC_ITCFMUL_LBIT)
#define MSC_ITCFMUL_10MHZ					(0x4 << MSC_ITCFMUL_LBIT)

#define MSC_ITCFVAL_HBIT					(9)
#define MSC_ITCFVAL_LBIT					(0)
#define MSC_ITCFVAL_MASK					GENMASK(MSC_ITCFVAL_HBIT, MSC_ITCFVAL_LBIT)

/* CQCFG */
#define MSC_DCMD_EN_BIT					BIT(12)
#define MSC_DCMD_DATA						(0)
#define MSC_DCMD_CMD						(1)

#define MSC_TASK_DESC_SIZE_BIT				BIT(8)
#define MSC_TASK_DESC_SIZE_64				(0)
#define MSC_TASK_DESC_SIZE_128				(1)

#define MSC_CQ_EN_BIT						BIT(0)
#define MSC_CQ_DISABLE						(0)
#define MSC_CQ_ENABLE						(1)

/* CQCTL */
#define MSC_CLR_ALL_TASKS_BIT				BIT(8)
#define MSC_CLR_ALL_TASKS_DISABLE			(0)
#define MSC_CLR_ALL_TASKS_ENABLE			(1)

#define MSC_HALT_BIT						BIT(0)
#define MSC_HALT_ENABLE					(0)
#define MSC_HALT_DISABLE					(1)

/* CQIS */
#define MSC_TCL_BIT						BIT(3)
#define MSC_TCL_FALSE						(0)
#define MSC_TCL_TRUE						(1)

#define MSC_RED_BIT						BIT(2)
#define MSC_RED_FALSE						(0)
#define MSC_RED_TRUE						(1)

#define MSC_TCC_BIT						BIT(1)
#define MSC_TCC_FALSE						(0)
#define MSC_TCC_TRUE						(1)

#define MSC_HAC_BIT						BIT(0)
#define MSC_HAC_FALSE						(0)
#define MSC_HAC_TRUE						(1)

/* CQISE */
#define MSC_TCL_STE_BIT					BIT(3)
#define MSC_TCL_STE_DISABLE				(0)
#define MSC_TCL_STE_ENABLE					(1)

#define MSC_RED_STE_BIT					BIT(2)
#define MSC_RED_STE_DISABLE				(0)
#define MSC_RED_STE_ENABLE					(1)

#define MSC_TCC_STE_BIT					BIT(1)
#define MSC_TCC_STE_DISABLE				(0)
#define MSC_TCC_STE_ENABLE					(1)

#define MSC_HAC_STE_BIT					BIT(0)
#define MSC_HAC_STE_DISABLE				(0)
#define MSC_HAC_STE_ENABLE					(1)

/* CQISGE */
#define MSC_TCL_SGE_BIT					BIT(3)
#define MSC_TCL_SGE_DISABLE				(0)
#define MSC_TCL_SGE_ENABLE					(1)

#define MSC_RED_SGE_BIT					BIT(2)
#define MSC_RED_SGE_DISABLE				(0)
#define MSC_RED_SGE_ENABLE					(1)

#define MSC_TCC_SGE_BIT					BIT(1)
#define MSC_TCC_SGE_DISABLE				(0)
#define MSC_TCC_SGE_ENABLE					(1)

#define MSC_HAC_SGE_BIT					BIT(0)
#define MSC_HAC_SGE_DISABLE				(0)
#define MSC_HAC_SGE_ENABLE					(1)

/* CQIC */
#define MSC_INTC_EN_BIT					BIT(31)
#define MSC_INTC_ENABLE					(0)
#define MSC_INTC_DISABLE					(1)

#define MSC_INTC_STAT_BIT					BIT(20)
#define MSC_INTC_STAT_NOT_COUNTED			(0)
#define MSC_INTC_STAT_COUNTED				(1)

#define MSC_INTC_RST_BIT					BIT(16)
#define MSC_INTC_RST_DISABLE				(0)
#define MSC_INTC_RST_ENABLE				(1)

#define MSC_INTC_TH_WEN_BIT				BIT(15)
#define MSC_INTC_TH_WEN_DISABLE			(0)
#define MSC_INTC_TH_WEN_ENABLE				(1)

#define MSC_INTC_TH_HBIT					(12)
#define MSC_INTC_TH_LBIT					(8)
#define MSC_INTC_TH_MASK					GENMASK(MSC_INTC_TH_HBIT, MSC_INTC_TH_LBIT)

#define MSC_TOUT_VAL_WEN_BIT				BIT(7)
#define MSC_TOUT_VAL_WEN_DISABLE			(0)
#define MSC_TOUT_VAL_WEN_ENABLE			(1)

#define MSC_TOUT_VAL_HBIT					(6)
#define MSC_TOUT_VAL_LBIT					(0)
#define MSC_TOUT_VAL_MASK					GENMASK(MSC_TOUT_VAL_HBIT, MSC_TOUT_VAL_LBIT)

/* CQSSC1 */
#define MSC_SQSCMD_BLK_CNT_HBIT			(19)
#define MSC_SQSCMD_BLK_CNT_LBIT			(16)
#define MSC_SQSCMD_BLK_CNT_MASK			GENMASK(MSC_SQSCMD_BLK_CNT_HBIT, MSC_SQSCMD_BLK_CNT_LBIT)

#define MSC_SQSCMD_IDLE_TMR_HBIT			(15)
#define MSC_SQSCMD_IDLE_TMR_LBIT			(0)
#define MSC_SQSCMD_IDLE_TMR_MASK			GENMASK(MSC_SQSCMD_IDLE_TMR_HBIT, MSC_SQSCMD_IDLE_TMR_LBIT)

/* CQSSC1 */
#define MSC_SQSCMD_RCA_HBIT				(15)
#define MSC_SQSCMD_RCA_LBIT				(0)
#define MSC_SQSCMD_RCA_MASK				GENMASK(MSC_SQSCMD_RCA_HBIT, MSC_SQSCMD_RCA_LBIT)

/* CQTERRI */
#define MSC_TRANS_ERR_FIFLDS_VALID_BIT		BIT(31)
#define MSC_TRANS_ERR_FIFLDS_VALID_IGNORE	(0)
#define MSC_TRANS_ERR_FIFLDS_VALID_CHECK	(1)

#define MSC_TRANS_ERR_TASKID_HBIT			(28)
#define MSC_TRANS_ERR_TASKID_LBIT			(24)
#define MSC_TRANS_ERR_TASKID_MASK			GENMASK(MSC_TRANS_ERR_TASKID_HBIT, MSC_TRANS_ERR_TASKID_LBIT)

#define MSC_TRANS_ERR_CMD_INDX_HBIT		(21)
#define MSC_TRANS_ERR_CMD_INDX_LBIT		(16)
#define MSC_TRANS_ERR_CMD_INDX_MASK		GENMASK(MSC_TRANS_ERR_CMD_INDX_HBIT, MSC_TRANS_ERR_CMD_INDX_LBIT)

#define MSC_RESP_ERR_FIELDS_VAILD_BIT		BIT(15)
#define MSC_RESP_ERR_FIFLDS_VALID_IGNORE	(0)
#define MSC_RESP_ERR_FIFLDS_VALID_CHECK	(1)

#define MSC_RESP_ERR_TASKID_HBIT			(18)
#define MSC_RESP_ERR_TASKID_LBIT			(14)
#define MSC_RESP_ERR_TASKID_MASK			GENMASK(MSC_RESP_ERR_TASKID_HBIT, MSC_RESP_ERR_TASKID_LBIT)

#define MSC_RESP_ERR_CMD_INDX_HBIT			(5)
#define MSC_RESP_ERR_CMD_INDX_LBIT			(0)
#define MSC_RESP_ERR_CMD_INDX_MASK			GENMASK(MSC_RESP_ERR_CMD_INDX_HBIT, MSC_RESP_ERR_CMD_INDX_LBIT)

/* CQCRI */
#define MSC_CMD_RESP_INDX_HBIT				(5)
#define MSC_CMD_RESP_INDX_LBIT				(0)
#define MSC_CMD_RESP_INDX_MASK				GENMASK(MSC_CMD_RESP_INDX_HBIT, MSC_CMD_RESP_INDX_LBIT)

/* EMMC_CTRL_R */
#define MSC_CQE_PREFETCH_DISABLE_BIT		BIT(10)
#define MSC_CQE_PREFETCH_ENABLE			(0)
#define MSC_CQE_PREFETCH_DISABLE			(1)

#define MSC_CQE_ALGO_SEL_BIT							BIT(9)
#define MSC_CQE_ALGO_SEL_PRI_REORDER_PLUS_FCFS			(0)
#define MSC_CQE_ALGO_SEL_FCFS_ONLY						(1)

#define MSC_ENH_STROBE_ENABLE_BIT			BIT(8)
#define MSC_ENH_STROBE_NO_STB_FOR_CMD		(0)
#define MSC_ENH_STROBE_ENH_STB_FOR_CMD		(1)

#define MSC_DISABLE_DATA_CRC_CHK_BIT		BIT(1)
#define MSC_DISABLE_DATA_CRC_CHK_ENABLE	(0)
#define MSC_DISABLE_DATA_CRC_CHK_DISABLE	(1)

#define MSC_CARD_IS_EMMC_BIT				BIT(0)
#define MSC_CARD_IS_EMMC_NON_EMMC_CARD		(0)
#define MSC_CARD_IS_EMMC_EMMC_CARD			(1)

/* BOOT_CTRL_R */
#define MSC_BOOT_TOUT_CNT_HBIT				(15)
#define MSC_BOOT_TOUT_CNT_LBIT				(12)
#define MSC_BOOT_TOUT_CNT_MASK				GENMASK(MSC_BOOT_TOUT_CNT_HBIT, MSC_BOOT_TOUT_CNT_LBIT)

#define MSC_BOOT_ACK_ENABLE_BIT			BIT(8)
#define MSC_BOOT_ACK_ENABLE_FALSE			(0)
#define MSC_BOOT_ACK_ENABLE_TRUE			(1)

#define MSC_VALIDATE_BOOT_BIT				BIT(7)
#define MSC_VALIDATE_BOOT_FALSE			(0)
#define MSC_VALIDATE_BOOT_TRUE				(1)

#define MSC_MAN_BOOT_EN_BIT				BIT(0)
#define MSC_MAN_BOOT_DIS					(0)
#define MSC_MAN_BOOT_EN					(1)

/* GP_IN_R */


/* GP_OUT_R */



#endif /* __MMC_H__ */
